Signed-off-by: Richard Henderson <richard.hender...@linaro.org> --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 23 ++++++++++++++--------- 2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a188452d2e..dd0ed3a993 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -171,6 +171,9 @@ MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0 UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc +UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0 +SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0 + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7e2a74a816..6ea857d8ee 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -53,6 +53,8 @@ #define gen_helper_write_softint(E, S) qemu_build_not_reached() #define gen_helper_saved ({ qemu_build_not_reached(); NULL; }) #define gen_helper_restored ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() +#define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached() #endif /* Dynamic PC, must exit to main loop. */ @@ -685,6 +687,16 @@ static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) gen_op_multiply(dst, src1, src2, 1); } +static void gen_op_udivx(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_udivx(dst, tcg_env, src1, src2); +} + +static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_sdivx(dst, tcg_env, src1, src2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -4233,6 +4245,8 @@ TRANS(XORN, ALL, do_arith, a, CC_OP_LOGIC, tcg_gen_eqv_tl, NULL) TRANS(MULX, 64, do_arith, a, 0, tcg_gen_mul_tl, tcg_gen_muli_tl) TRANS(UMUL, MUL, do_arith, a, CC_OP_LOGIC, gen_op_umul, NULL) TRANS(SMUL, MUL, do_arith, a, CC_OP_LOGIC, gen_op_smul, NULL) +TRANS(UDIVX, 64, do_arith, a, 0, gen_op_udivx, NULL) +TRANS(SDIVX, 64, do_arith, a, 0, gen_op_sdivx, NULL) static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a) { @@ -4755,11 +4769,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn); switch (xop & ~0x10) { -#ifdef TARGET_SPARC64 - case 0xd: /* V9 udivx */ - gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_src2); - break; -#endif case 0xe: /* udiv */ CHECK_IU_FEATURE(dc, DIV); if (xop & 0x10) { @@ -4897,10 +4906,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) gen_store_gpr(dc, rd, dst); break; } - case 0x2d: /* V9 sdivx */ - gen_helper_sdivx(cpu_dst, tcg_env, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x2e: /* V9 popc */ tcg_gen_ctpop_tl(cpu_dst, cpu_src2); gen_store_gpr(dc, rd, cpu_dst); -- 2.34.1