[PATCH 07/19] cpus: Filter for target specific CPU (riscv)

[Philippe Mathieu-Daudé]

Enforce qemu_get_cpu() to return RISCV CPUs in RISCV specific files.

Mechanical change using the following coccinelle script:

  @@ expression index; @@
  -   qemu_get_cpu(index, NULL)
  +   qemu_get_cpu(index, TYPE_RISCV_CPU)

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
 hw/intc/sifive_plic.c | 2 +-
 hw/riscv/boot.c       | 2 +-
 hw/riscv/opentitan.c  | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 3e2534ac04..ea0e7af16e 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -499,7 +499,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char 
*hart_config,
 
     for (i = 0; i < plic->num_addrs; i++) {
         int cpu_num = plic->addr_config[i].hartid;
-        CPUState *cpu = qemu_get_cpu(cpu_num, NULL);
+        CPUState *cpu = qemu_get_cpu(cpu_num, TYPE_RISCV_CPU);
 
         if (plic->addr_config[i].mode == PLICMode_M) {
             qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index ea733b3df1..1d004660d4 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -49,7 +49,7 @@ char *riscv_plic_hart_config_string(int hart_count)
     int i;
 
     for (i = 0; i < hart_count; i++) {
-        CPUState *cs = qemu_get_cpu(i, NULL);
+        CPUState *cs = qemu_get_cpu(i, TYPE_RISCV_CPU);
         CPURISCVState *env = &RISCV_CPU(cs)->env;
 
         if (kvm_enabled()) {
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index e98361de19..106ef5d2d0 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -190,7 +190,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, 
Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
 
     for (i = 0; i < ms->smp.cpus; i++) {
-        CPUState *cpu = qemu_get_cpu(i, NULL);
+        CPUState *cpu = qemu_get_cpu(i, TYPE_RISCV_CPU);
 
         qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
                               qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
@@ -223,7 +223,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, 
Error **errp)
                        0, qdev_get_gpio_in(DEVICE(&s->plic),
                        IBEX_TIMER_TIMEREXPIRED0_0));
     qdev_connect_gpio_out(DEVICE(&s->timer), 0,
-                          qdev_get_gpio_in(DEVICE(qemu_get_cpu(0, NULL)),
+                          qdev_get_gpio_in(DEVICE(qemu_get_cpu(0, 
TYPE_RISCV_CPU)),
                                            IRQ_M_TIMER));
 
     /* SPI-Hosts */
-- 
2.41.0