Index: target-mips/helper.c
===================================================================
RCS file: /cvsroot/qemu/qemu/target-mips/helper.c,v
retrieving revision 1.24
diff -u -r1.24 helper.c
--- target-mips/helper.c	22 Jan 2007 20:50:42 -0000	1.24
+++ target-mips/helper.c	13 Feb 2007 21:24:28 -0000
@@ -41,12 +41,12 @@
 static int map_address (CPUState *env, target_ulong *physical, int *prot,
                         target_ulong address, int rw, int access_type)
 {
+    uint8_t ASID = env->CP0_EntryHi & 0xFF;
     int i;
 
     for (i = 0; i < env->tlb_in_use; i++) {
         tlb_t *tlb = &env->tlb[i];
         /* 1k pages are not supported. */
-        uint8_t ASID = env->CP0_EntryHi & 0xFF;
         target_ulong mask = tlb->PageMask | 0x1FFF;
         target_ulong tag = address & ~mask;
         int n;
Index: target-mips/op.c
===================================================================
RCS file: /cvsroot/qemu/qemu/target-mips/op.c,v
retrieving revision 1.22
diff -u -r1.22 op.c
--- target-mips/op.c	24 Jan 2007 18:01:23 -0000	1.22
+++ target-mips/op.c	13 Feb 2007 21:24:28 -0000
@@ -1340,7 +1340,7 @@
 
     /* 1k pages not implemented */
     /* Ignore MIPS64 TLB for now */
-    val = (int32_t)T0 & 0xFFFFE0FF;
+    val = (target_ulong)(int32_t)T0 & ~(target_ulong)(uint32_t)0x1F00;
     old = env->CP0_EntryHi;
     env->CP0_EntryHi = val;
     /* If the ASID changes, flush qemu's TLB.  */
Index: target-mips/op_helper.c
===================================================================
RCS file: /cvsroot/qemu/qemu/target-mips/op_helper.c,v
retrieving revision 1.28
diff -u -r1.28 op_helper.c
--- target-mips/op_helper.c	24 Jan 2007 01:47:51 -0000	1.28
+++ target-mips/op_helper.c	13 Feb 2007 21:24:29 -0000
@@ -395,7 +395,7 @@
 
     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
     tlb = &env->tlb[idx];
-    tlb->VPN = env->CP0_EntryHi & (int32_t)0xFFFFE000;
+    tlb->VPN = env->CP0_EntryHi & ~(target_ulong)(uint32_t)0x1FFF;
     tlb->ASID = env->CP0_EntryHi & 0xFF;
     tlb->PageMask = env->CP0_PageMask;
     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;