Hello All,
this is the first (and most trivial) part of my MIPS-related patchset.
It adds an explanatory comment and removes some bits of dead code.
Thiemo
Index: cpu-exec.c
===================================================================
--- cpu-exec.c.orig 2006-05-15 01:13:14.000000000 +0100
+++ cpu-exec.c 2006-05-15 01:18:21.000000000 +0100
@@ -561,6 +561,8 @@
#elif defined(TARGET_SH4)
/* XXXXX */
#endif
+ /* Don't use the cached interupt_request value,
+ do_interrupt may have updated the EXITTB flag. */
if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
/* ensure that no TB jump will be modified as
Index: target-mips/helper.c
===================================================================
--- target-mips/helper.c.orig 2006-05-15 01:13:14.000000000 +0100
+++ target-mips/helper.c 2006-05-15 01:18:21.000000000 +0100
@@ -219,7 +219,6 @@
exception = EXCP_TLBS;
else
exception = EXCP_TLBL;
- error_code = 0;
break;
case -4:
/* TLB match but 'D' bit is cleared */
@@ -350,7 +349,6 @@
cause = 4;
goto set_EPC;
case EXCP_TLBL:
- case EXCP_TLBF:
cause = 2;
if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
offset = 0x000;
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