On 9/3/25 12:04, BALATON Zoltan wrote:
On Sat, 8 Mar 2025, Philippe Mathieu-Daudé wrote:
Per the MPC8569E reference manual, its SDHC I/O range is 4KiB
wide, mapped in big endian order, and it only accepts 32-bit
aligned access. Set the default register reset values.
Reported-by: BALATON Zoltan <bala...@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
include/hw/sd/sdhci.h | 2 ++
hw/sd/sdhci.c | 37 ++++++++++++++++++++++++++++++++++++-
2 files changed, 38 insertions(+), 1 deletion(-)
-/* --- qdev i.MX eSDHC --- */
+/* --- Freescale eSDHC (MPC8569ERM Rev.2 from 06/2011) --- */
+
+static const MemoryRegionOps fsl_esdhc_mmio_ops = {
+ .read = sdhci_read,
+ .write = sdhci_write,
+ .valid = {
+ .min_access_size = 4,
Does this need max access too? Maybe it could work with 8 and likely
nothing would try to access more than 4 so probably does not matter.
Per the reference manual (chapter 16):
All eSDHC registers must be accessed as aligned 4-byte quantities.
Accesses to the eSDHC registers that are less than 4-bytes are not
supported.
There is no precision on max_access_size.
Regards,
BALATON Zoltan
