On 03/02/2015 07:38 AM, MRAB wrote:
On 2015-03-02 04:49, Dave Angel wrote:
On 03/01/2015 08:59 PM, MRAB wrote:
On 2015-03-02 01:37, Dennis Lee Bieber wrote
The 16 bit address bus permitted addressing of 64k words. On most
processors, that was 64k bytes, though I know one Harris had no bytes,
but every memory access was 16 bits. It therefore had the equivalent of
128k bytes. Likewise I believe some of the DEC and DG minis had 128k
bytes of addressability.
I have (or had, not sure where it is!) a manual of the TMS9900
processor, and I'm sure it addresses 64k _bytes_.
Wikipedia says "65,536 bytes or 32,768 words".
Like I said, on most processors, it was 64k bytes.
interestingly enough I know of one architecture which used 128k for the
8-bit Z80, even though that processor only had 16 address lines. Being
a server, the code was mostly static, and fit in 64k. But they also
wanted 64k for data. So they used one of the processor status lines as
a select between two banks of memory. When the processor was fetching an
instruction, it got it from bank 0, while if it was fetching or writing
data, it went to bank 1. Obviously they had a mode where it read and
wrote from bank 0 as data, both for bootstrapping, and for overlays or
whatever.
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DaveA
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