This was part of an earlier discussion in this forum. I want to correct the impression created by Lawrence D'Oliveiro that those who implemented stacks were not designing for efficiency.
> What I can say is that for scientific/engineering calculations the RPN of > KDF9 was Great because assembler was no harder than using algol60 for the > calculations part of the problems I worked on. Lawrence D'Oliveiro ldo at geek-central.gen.new_zealand <mailto:python-list%40python.org?Subject=Re%3A%20Good%20books%20in%20computer%20science%3F&In-Reply-To=%3Ch1mo5n%24dlq%243%40lust.ihug.co.nz%3E> Mon Jun 22 03:52:55 CEST 2009 Unfortunately, we had to learn the hard way that machine instruction sets must be designed for efficiency of execution, not ease of use by humans. Stack-based architectures, for all their charm, cannot match register-based ones in this regard. FWIW: "Efficiency" is a slippery notion with contextual connotations. KDF9 had two stacks in its CPU. (The SJNS and the Nesting Store or Nest - see Eric's thesis.) I am not suggesting that you are ill-informed, but that stacks are insufficiently represented in the literature. The use of call return stacks to support subroutine returns is almost universal. For the evaluation of arithmetical expressions, the use of hardware stacks is the most efficient. From what I have read, it is compiler writers who find it hard to emulate the efficiencies achieved by assembler programmers. Are hardware designers considering the compiler writers' problems when they design their hardware? This would be heavy irony indeed. That is why stacks came into existence in the first place. Regards, Phil References: http://is.uwaterloo.ca/Eric_LaForest_Thesis.pdf discusses the confusion of first and second generation stack-based architectures. It includes a rebuttal of the arguments against stack computers, cited by Hennessy and Patterson, showing that they are applicable to the first generation of stack computers, but not the second. Christopher Bailey's "Optimisation Techniques for Stack-Based Processors", PhD thesis, University of Teesside, UK, July 1996, Amongst other things, analyzes the use of stack buffers to reduce memory traffic.
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