Blubaugh, David A. wrote: > because labview is neither free nor open source. Labview is not the > route to go for someone like me who has no real capital. > > I thought you were doing your master thesis ? And LabView is almost for free, for people linked in anyway to an educational institute !
But to be honest, I don't like LabView very much and would love to see an open source alternative ! succes, cheers, Stef Mientki > David Blubaugh > > > > > > > > > -----Original Message----- > From: Stef Mientki [mailto:[EMAIL PROTECTED] > Sent: Thursday, February 14, 2008 1:25 PM > To: python-list@python.org > Subject: Re: SAGE for FPGA development > > Blubaugh, David A. wrote: > >> Bill, >> >> >> Let me first say that my FPGA experiences are of the following nature: >> >> 1.) Developed control algorithms onto a FPGA that were utilized to >> control a switch-reluctance motor (three-phase as well six-phase). >> >> 2.) I am currently in the process of developing a specialized >> Multidimensional FFT processor that can be utilized to determine the >> frequency content and angle of arrival of a target via a linear sensor >> array. >> >> I believe that you are deeply mistaken about that I would be the only >> person to use such a system. The FPGA market will only increase as >> > more > >> embedded systems utilize more and more FPGAs for the processing needs, >> since embedded system are being task with more computationally >> > intensive > >> tasks, such as for example, image digital signal processing within >> portable digital cameras. Electrical and Computer Engineers could >> > start > >> to utilize SAGE for system programming and development, not just only >> mathematicians or physicists doing their own selected work. >> >> Also, I think that you may have the wrong idea of porting SAGE to be >> executed within a FPGA. What I had in mind was to have MyHDL embedded >> within SAGE, where sage could handle the graphical plot outputs of >> > what > >> is being generated by MyHDL. To be absolutely clear, SAGE could be >> > used > >> to handle the graphs for the simulation side of what the logic that is >> being generated by MyHDL embedded within the SAGE framework. This >> > could > >> help in testing algorithms as they are being generated into verilog >> > FPGA > >> logic, by having a graphical experience within the entire development >> process. >> >> >> If you have any more additional questions, please contact me as soon >> > as > >> possible. >> >> >> > Why not use LabView, it seems to have good FPGA support ? > cheers, > Stef > > > > This e-mail transmission contains information that is confidential and may be > privileged. It is intended only for the addressee(s) named above. If you > receive this e-mail in error, please do not read, copy or disseminate it in > any manner. If you are not the intended recipient, any disclosure, copying, > distribution or use of the contents of this information is prohibited. Please > reply to the message immediately by informing the sender that the message was > misdirected. After replying, please erase it from your computer system. Your > assistance in correcting this error is appreciated. > > > -- http://mail.python.org/mailman/listinfo/python-list
