Check out: http://home.capecod.net/~pstevens/FPGAAuto.pdf
This was all autogenerated from a higher level VHDL description by the FPGA to PCB Project Wizard. ---Phil R> Hi Phillip, R> Could you just elaborate a little on >>The automatic generation of the *entire* FPGA's schematic sheet, >>drawing all the wires, assigning nets to the wires, creating >>the off sheet ports, creating the pin constraints file, and the FPGA pin >>assignments can be passed down to the PCB automagically. It's all really >>very nice. R> I assume that the schematic sheet that is created is simply a block with R> all the I/Os brought out as named nets? i.e. it doesn't attempt to R> interpret your VHDL and produce a schematic representation of your code? R> I'm not arguing, just trying to see where the big benefit is. Right now I R> use the Xilinx software, and most design entry is via their schematic R> editor (crappy as it is!)and as little as possible in plain VHDL. R> Constraint entry is done on the schematic. Granted that I have to manually R> create a library entry with pin names and numbers in Protel, and I have to R> edit that every time I change something in the design, I agree that it R> would be nice to have it done automatically, but... am I missing something R> more? R> Thanks for your input. R> Roger * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
