i assume this is near a bd edge? the bd outline and keepout don't necessarily need to be coincident
sometimes we either break the keepout in this situation (if the board is routed) or just bend it out a little to make the clearance negative clearances don't work Dennis Saputelli Ray Mitchell wrote: > > Hello, > > I have a clearance constraint between a trace on the keepout layer and a > component on the top layer set to 0mil (I've also tried -1mil) but it still > gives me a DRC error between the keepout trace and the component pad that > sits on top of it. This is obviously not the correct approach. Suggestions? > > Thanks, > Ray Mitchell > > Ray Mitchell > Engineer, Code 2732 > SPAWAR Systems Center > San Diego, CA. 92152 > (619)553-5344 > [EMAIL PROTECTED] > -- _______________________________________________________________________ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st Street Fax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
