> -----Original Message----- > From: Brooks,Bill [mailto:[EMAIL PROTECTED] > Sent: Monday, April 12, 2004 6:43 PM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Would it not be nice? > > The key thing here John, may be, that Altium will need to > have a separate group of people to service the needs of their > "Simulation/Nanoboard" types from the PCB/SCH types. They > certainly have more issues to respond to.
Bill This is true, unfortunately the bias seems to be towards the FPGA tools, I can understand why I guess, a lot more to consider than in just Capture/Layout but it has resulted in an over complex capture and layout environment with some clunky features, due to a simplified GUI approach not being practical for FPGA design as the FPGA design cycle is effectively within a software (scripted & text entry) environment. I do design as well, although my main focus is layout, I also deal with some major IC vendors for which I do the development/test boards and pre-layout analysis so they can decide on chip pin-out, similar to one of the target tasks of the new 2004 suite. To do this all I would have liked would have been to be able to import/export a ASIC pin list in ASCII, along the same idea as Orcad has done for years. Pin / Gate swapping might seem a small thing, but I would have been happier to see this feature in 2004 than new FPGA tools. > A full suite of tools says to me.. 'one size fits all'... or > more accurately would be like saying, 'This is the Family > Pack entertainment system, oh, you only wanted a tennis > racket? Well just you can store the ping pong table and the > billiards, The baseball bat and gloves, and the bonus camping > accessories in your garage and use them later...sorry, we > can't break up the set, there are no discounts'... > > Most of the PCB designers today don't need the simulation > tools, or the FPGA tools. Although we may need them in the > future when the boards we have to do are too complex to > properly layout, the simulation tools might help us deal with > impedance issues, line lengths, crosstalk, EMI, etc. See my above comment, I already do that anyway and have had some success in having ASIC design groups, amongst others, change pinouts (sometimes also test benches / simulations to suit external layout criteria) so that the test boards are ready and waiting for the devices at tape-out. In some cases the boards have been adopted as reference design boards and SDKs. Memory interfaces are the prime example, 64 bit/66MHz PCI being another, being able to have the IC designer move RAS/CAS/OE... because of layout needs makes life a lot easier for the layout engineer! How many times have we said 'who decided the pin locations on this damned device, they surely have not tried to lay it out first!' Altium seem to want to do a similar here, give the designer of FPGA the power to do this, I can see their goal with FPGA, rather than ASIC, I am just not a believer (yet) as I think the disciplines are too far removed from each other to be truly effective and very rarely completely under one persons control. I am used to a team environment, some say spoiled, but I am happy to play and share with others, it works better that way, a mans gotta know his limitations. > Besides, Xilinx gives away a very nice development package to > folks that want to work with their FPGA products... we > already have one. But I don't use it... the EE/FPGA engineer > uses it. The PCB guy(me)just does boards and schematics. And > the EE/FPGA guy does not layout the boards. But you can still control / advise on pinout if given the chance. > snip < > The ability to convert other CAD systems databases to Protel > is also a very powerful tool and should have been supported > more completely as the product has evolved. So many more > customers 'jump' to a product when it offers to convert their > old legacy databases into their new purchased format. But a lot of the importers planned were never implemented, the main concentration is Orcad. I had conversations a long time ago with Protel on a Cadstar importer, it never appeared. > I believe Altium/Protel has lost its 'common sense'... or > maybe PCB designer sense at the very least. Which is a great pity, as from my understanding, I am sure Mr Lomax will correct me if I am wrong (as he seems pretty hot on Protel history) that Protel tools were first created out of ones mans frustrations with the PCB layout tools available at the time, being clunky, inefficient and hard to use, so Protel was born. Circle of life eh? :-) John > > Bill Brooks > PCB Design Engineer , C.I.D., C.I.I. > Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 > > -----Original Message----- > From: John A. Ross [RSDTV] [mailto:[EMAIL PROTECTED] > Sent: Sunday, April 11, 2004 4:33 PM > To: 'Protel EDA Forum' > Subject: [PEDA] Would it not be nice? > > > Proper pin / gate swapping, a VERY high wish on all users > wish list, still > has not made it, but would have been nice, but we have FPGA > tools, so much > better than pin / gate swapping. > > John > > > > -----Original Message----- > > From: Nick Martin [mailto:[EMAIL PROTECTED] > > Sent: Monday, April 12, 2004 12:00 AM > > To: DXP Technical Forum > > Subject: Re: [dxp] NanoBoard > > > > snipped < > > > > I would be interested to know why you feel the need to use > > ISE and what areas of it are most interesting / useful to you. > > > > Best Regards, > > > > Nick > > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
