On 2018/08/28 15:11, Alessandro DE LAURENZIS wrote: > Hi Stuart, > > On 2018-08-28 13:46, Stuart Henderson wrote: > [...] > > I've reworded DESCR a bit, I think this flows a bit better? > > > > == > > graywolf is a tool for placement and routing used as part of a tool > > chain for synthesizing digital circuits (VLSI), mainly intended for use > > used together with qflow (http://opencircuitdesign.com/qflow/). > > This is definitely confusing: synthesis isn't involved during placement (and > routing). Moreover, graywolf (differently from TimberWolf) doesn't have > routing algorithms at all. > > Maybe: > > graywolf is a program for placement of VLSI digital circuits, > mainly intended as part of qflow tool-chain > (http://opencircuitdesign.com/qflow/).
Yes that sounds good. > > > > It is a fork of the last open-source version of TimberWolf (which is > > now commercial software) and has been modified to streamline the build > > process and make it behave more as a standard command-line tool. > > > > It is based on the general combinatorial optimization technique known > > as simulated annealing and is suitable for standard cell, macro/custom > > cell, and gate-array professional-grade placement. > > == > > This part is ok, I think. > > > > > > > Is there anything simple that can be done about all the "format > > specifies > > type 'int' but the a rgument has type 'INT' (aka 'long') [-Wformat]" > > warnings during build? > > Hope someone with more experience than me can answer to this point, > nonetheless I'll have a look. > > All the best > > -- > Alessandro DE LAURENZIS > [mailto:[email protected]] > Web: http://www.atlantide.t28.net > LinkedIn: http://it.linkedin.com/in/delaurenzis >
