Hi List! I hope everyone is safe and in good health.
Even though I don't login to freenode these days, but I made it a habit to check the channel everyday :) And what I read yesterday is the reason for this email. I saw some message about PilMCU so let me provide some answers here: "... if Geo has or will ever post his FPGA picolisp code for the hardware Pil machine he posted to youtube some years ago" -> As of the moment, I don't recommend to post it yet because of the following reasons: * The code is still messy (both PilASM assembler and Verilog), contains temporary codes for debugging * The implementation is still unoptimized * The Verilog code is not yet designed for portability to other FPGA vendor and other FPGA boards But don't worry, I will post it as soon as I get all these sorted out. BUT, if you really want to see the code for reference, I can email it to you or anyone interested and discuss how the development process was done as well the whole approach. "... Seems he stopped it" -> I know it feels like that way because I did not provide any update for a long time, but I would like to say that it is not yet stopped, but its still on-hold. It's still difficult for me to find extra time for this but I believe sometime soon I can get back on this. My motivation to have this done is still the same as the beginning because I still believe this will address most of my frustration on current firmware development work flow. "... I would expect better performance, since you can in theory implement lisp functions and run many of them in parallel" -> This is true and this is actually one of the main motivator for me. An analogy that can back this theory is bitcoin mining, from CPU -> GPU -> FPGA -> ASIC, arranged as slowest to fastest. It's still difficult to implement lisp with parallel computing in mind but I have some other ideas that I would like to try and show that this approach is indeed interesting to venture. The reason why current implementation is slow is because of the following: * The approach of implementation did not fully utilize the advantage of FPGA over off the shelf CPU or MCU * The implementation is not optimized due to no proper experience before * 50Mhz clock made it feel slower :) But as of the moment, I keep taking notes on how to resolve all these as well as plan how to implement it. For now, these are my goal for next PilMCU version which I want to call uPil (u for micro): * Cell processing directly in hardware * Reduce primitives to a few core primitive to fit Cell processing on any FPGA with decent logic size * Use FRAM as storage of Pil codes in Cell format and run code from FRAM * Use NOR Flash or external SD card as storage of Pil codes in ASCII format with DB as filesystem * Use internal memory of FPGA as RAM which will achieve register like speed * Only Verilog code needed, no need PilASM assembler * Must run on three major FPGA vendors with no code modification Im not sure if all these are feasible but I think it will be, will see how it goes. I was also keeping an eye on other implementors of lisp on of the shelf MCU, here are the latest ones: 1. http://www.ulisp.com/ 2. https://www.youtube.com/watch?v=GWr4iQfc0uw&list=PLQu9CQjHyYejctK-zxYbAC8kWUTkgcjsA&index=30&t=116s https://icfp20.sigplan.org/details/scheme-2020-papers/3/Running-Scheme-On-Bare-Metal-Experience-Report- 3. https://lambdachip.com/index/ I was also planning to have PilMCU be remotely access during PilCon, let me try get it back to working state and see how I can setup remote access, I got TeamViewer on my PC so will see. I remember there was someone trying to port PilOS on RPi? Ok sorry for this long email, before I'll end let me comment of some recent issue that I read also, about unstable email as well as the freenode issue? Hmm what about developing email server and/or irc server using PicoLisp? Would this be a nice group project? It's like hitting two birds in one stone because: first it will address the issues, second it will serve as another demo that can help promote PicoLisp to the outside? or instead of centralized, how about something like those of fediverse or matrix? Anyway just some ideas before going to bed :) Have a good weekend everyone, stay safe always and keep in touch, cheers! BR, Geo
