Just when you thought it was safe to go back in the water ...
According to my reading of the MIPS documentation, that architecture
requires explicit "sync" instructions to guarantee ordering of memory
accesses, just like PowerPC does. We have a "sync" now in the tas()
inline code that grabs a spinlock, but it seems to me that there has
to be one in the unlock code as well. Else you could have a situation
where a spinlock is released but updates of the shared memory variables
it's supposed to protect aren't yet written where other processors can
see 'em. In short it seems like this architecture needs S_UNLOCK just
like PowerPC's:
#define S_UNLOCK(lock) \
do \
{\
__asm__ __volatile__ (" sync \n"); \
*((volatile slock_t *) (lock)) = 0; \
} while (0)
This would only make a difference on multi-CPU MIPS machines, which are
probably not so thick on the ground that anyone would have noticed the
bug yet.
Comments?
regards, tom lane
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