På tirsdag 09. januar 2018 kl. 23:06:06, skrev Andres Freund <and...@anarazel.de <mailto:and...@anarazel.de>>: Hi,
On 2018-01-09 21:47:17 +0100, Andreas Joseph Krogh wrote: > Does PG use HW-accellerated crc if CPU supports it[1]? Yes we do, for WAL checksums. The page checksums are a different algorithm though, one which has the advantage of being SIMD compatible. The checksum computations have some impact, but if there's bigger impact it's much more likely to be related to the fact that some hint bit writes to a page now needs to be WAL logged. But SIMD-instructions are also HW-accellerated by modern CPUs IIUC? So, if these CRCs all are HW-accelerated the penalty chould be next to neglishable? -- Andreas Joseph Krogh CTO / Partner - Visena AS Mobile: +47 909 56 963 andr...@visena.com <mailto:andr...@visena.com> www.visena.com <https://www.visena.com> <https://www.visena.com>
