Jeff Clites <[EMAIL PROTECTED]> wrote: > But that loops back to a previous proposal of mine: If they're not > being preserved, and in fact need to be "synced" between caller and > callee, then having these registers physically located in the > interpreter structure, rather than in the bp-referenced frame, saves > all the copying, and makes it more obvious what's going on.
Well I answered that already. Having two distinct addressing schemes for volatile and non-volatile registers has a serious overhead for non-prederefed run cores. OTOH in the light of a recent discussion this approach could be an alternative. > JEff leo
