Dan Sugalski wrote: > Leopold Toetsch wrote: > > > > Can we really have e.g. odd aligned PMCs on stack? > > the specs are available *somewhere*, and we should see > about digging them up and getting a final answer one way > or another.
A gold mine of cpu specs: http://www.mit.edu/afs/sipb/contrib/doc/specs/ic/cpu/ Intel Architecture Software Development Manual - Volume 1: Basic Architecture http://www.mit.edu/afs/sipb/contrib/doc/specs/ic/cpu/x86/iapx-v1.pdf Chapter 4.2.2 Stack Alignment The stack pointer for a stack segment should be aligned on 16-bit (word) or 32-bit (double-word) boundaries, depending on the width of the stack segment. The D flag in the segment descriptor for the current code segment sets the stack-segment width (refer to Chapter 3, Protected-Mode Memory Managementof the Intel Architecture Software Developer's Manual, Volume 3). The PUSH and POP instructions use the D flag to determine how much to decrement or increment the stack pointer on a push or pop operation, respectively. When the stack width is 16 bits, the stack pointer is incremented or decremented in 16-bit increments; when the width is 32 bits, the stack pointer is incremented or decremented in 32-bit increments. The processor does not check stack pointer alignment. It is the responsibility of the programs, tasks, and system procedures running on the processor to maintain proper alignment of stack pointers. Misaligning a stack pointer can cause serious performance degradation and in some instances program failures. And also interesting: http://research.microsoft.com/users/jch/fftw-performance.html Tuning 64-bit floating point code on x86 using gcc, Visual C, and Intel C compilers -- Garrett Goebel IS Development Specialist ScriptPro Direct: 913.403.5261 5828 Reeds Road Main: 913.384.1008 Mission, KS 66202 Fax: 913.384.2180 www.scriptpro.com [EMAIL PROTECTED]
