>>>>> "n" == nick <[EMAIL PROTECTED]> writes:
n> Uri Guttman <[EMAIL PROTECTED]> writes:
>>
>> that is my concept of inline delivery. in the op dispatch loop, either a
>> counter is used or a special op (which was automatically code generated
>> is called and then all pending events (I/O, signals, timers, etc.) get
>> dispatched synchronously with the perl interpreter.
n> The special op is closest to what I mean, but still not as "tight"
n> as I meant. in Dan's "register based" machine the signal handler
n> would "save the program counter" and point it at what the "signal
n> (read interrupt) vector" pointed to - then "return" from the
n> handler carries on where you were.
i dunno this register machine you speak of. my guess it is analogous to
cpu architectures. even register cpus need a stack. so this would be
someway of passing around values other than on a stack.
but the question remains, what code triggers a signal handler? would you
put a test in the very tight loop of the the op dispatcher? or a simple
counter and a test every N loops? or make a special op that does the
test and possible trigger? i think all need to be supported and the
coder can select the trigger test mode with a pragma. so we can have two
different op dispatch loops (i am under the impression that that type of
thingie will be replaceable in perl6), one which does the event test and
trigger and the other doesn't (you need an event loop or the dispatch op
executed.
n> But if "runops" looked like:
n> while (PL_op = PL_next_op)
n> {
PL_op-> perform(); # assigns PL_next_op;
n> }
n> (Which is essentially FORTH-like) then there is little to get in a mess.
n> The above is simplistic - we need a way to "disable interrupts" too.
and where is the event test call made? or somehow the next op delivered
will be the next baseline op or the dispatch check op. that is basically
the same as my ideas above, just a different style loop.
uri
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