------- Forwarded Message
Date: Thu, 13 Sep 2007 14:46:31 -0700
From: Walter Bays <[EMAIL PROTECTED]>
Subject: Re: (fwd) Re: [perf-discuss] Project proposal: CPUfs
Jim Mauro wrote:
> Any processor technology that implements the notion of a thread or strand
> that is described as a CPU by Solaris is an issue. That's Niagara,
> Niagara-2,
> and all the OPL boxes. Similar problems are looming in the AMD and Intel
> space.
During any particular clock cycle do you consider a core to be busy if
there is an instruction active? Is it busier if there are four
instructions active instead of one? Is it equally busy whether the
instruction is in an execution unit, waiting on per-core cache, waiting
on per-chip cache, or waiting on memory? Is it any busier if it has both
an integer and a floating point instruction active? What if it's
handling instructions for a scout thread, is that active or inactive? If
there's one FP unit per 8 cores and it's active, which core gets to
count that as active? If some functional units may be dynamically
reconfigured then is a core which owns such a unit and isn't using it
any less busy than one which does not own such a unit?
Just being Devil's advocate. I don't doubt that you should be able to
improve the measurement significantly. I just think that the notion of
CPU utilization is a vague and processor dependent concept, and you
shouldn't expect to get any perfect answers.
"Everyone just needs to give 110 percent."
University of Connecticut basketball coach Jim Calhoun
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