Hi folks,
While investigating a performance problem in my prototype workspace, I
found that the dtlb-miss rate is about 16% higher than that of the
baseline, so I suspect that the high tlb miss could be the issue.
So, how can I get the statistics on the PC addresses when the tlb miss
happens? Can DTrace or some other facilities help here? Thank you in
advance!
- yxn
The attached in the sample trapstat output: (ignored the itlb column)
Mine:
cpu m size| dtlb-miss %tim dtsb-miss %tim |%tim
----------+-------------------------------+----
0 u 8k| 7399 0.3 0 0.0 | 0.3
0 u 64k| 0 0.0 0 0.0 | 0.0
0 u 512k| 0 0.0 0 0.0 | 0.0
0 u 4m| 0 0.0 0 0.0 | 0.0
- - - - - + - - - - - - - - - - - - - - - + - -
0 k 8k| 397423 14.5 237 0.0 |14.5
0 k 64k| 0 0.0 0 0.0 | 0.0
0 k 512k| 0 0.0 0 0.0 | 0.0
0 k 4m| 0 0.0 0 0.0 | 0.0
==========+===============================+====
ttl | 404822 14.7 237 0.0 |14.8
Baseline:
cpu m size| dtlb-miss %tim dtsb-miss %tim |%tim
0 u 8k| 8667 0.3 9 0.0 | 0.3
0 u 64k| 0 0.0 0 0.0 | 0.0
0 u 512k| 0 0.0 0 0.0 | 0.0
0 u 4m| 0 0.0 0 0.0 | 0.0
- - - - - + - - - - - - - - - - - - - - - + - -
0 k 8k| 342333 12.5 233 0.0 |12.6
0 k 64k| 0 0.0 0 0.0 | 0.0
0 k 512k| 0 0.0 0 0.0 | 0.0
0 k 4m| 21 0.0 0 0.0 | 0.0
==========+===============================+====
ttl | 351021 12.8 242 0.0 |12.9
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