> Also, to expand on the NUMA configuration I have in > mind: consider a system with 4 hypothetical Niagara+ > chips connected together (yes, original Niagara only > supports a Single-CMP). Each Niagara has its own > local memory controllers. Threads running on a chip > should ideally allocate physical memory addresses > from its local memory controllers whenever possible.
Connected together via a crossbar or Hypertransport like ring configuration? This message posted from opensolaris.org _______________________________________________ perf-discuss mailing list perf-discuss@opensolaris.org
