Pilot and PalmPilot units with 128k and 512k only use 8-bits
of the RAM memory bus. 1 meg units use 16-bit to access SDRAM.
I think all the current units can use a 16-bit RAM access.
Note that the 68EC000 core does not have any cache. I don't
think it even has fetch ahead (this is from memory of the block
diagram in a late 1970's issue of IEEE Micro on the M68000
architecture), but if so it's only 2 bytes deep. Since there
is no cache, most of the DragonBall's time is spent fetching
instructions. Thus there is absolute no advantage in interleaving
memory functionality since there is only one memory port and
it's instruction fetch limited. Most of the time, current Palm
devices are either napping, or fetching instructions (with
wait states.)
The timings are all available in the M68000 family programmers
reference manual. I think the Mot web site has pdf's available
here:
<http://ebus.mot-sps.com/ProdCat/psp/0,1250,MC68EZ328~M934310090795,00
.html#documentation>
IMHO. YMMV.
Ron Nicholson
HotPaw
http://www.hotpaw.com/rhn/hotpaw/
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