The kernel 6.6.69 backport the fixes of rockchip naneng-combphy
driver. But the dts changes of rk3568 have not been merged into
the linux mainline, so backport this to avoid broken rk3568.
Fixes: 89b2356 ("kernel: bump 6.6 to 6.6.69")
Link:
https://lore.kernel.org/all/173318214612.1403925.12222889205247999008.b4...@sntech.de/
Signed-off-by: Chukun Pan <amad...@jmu.edu.cn>
---
...dd-reset-names-for-combphy-on-rk3568.patch | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644
target/linux/rockchip/patches-6.6/035-v6.13-arm64-dts-rockchip-add-reset-names-for-combphy-on-rk3568.patch
diff --git
a/target/linux/rockchip/patches-6.6/035-v6.13-arm64-dts-rockchip-add-reset-names-for-combphy-on-rk3568.patch
b/target/linux/rockchip/patches-6.6/035-v6.13-arm64-dts-rockchip-add-reset-names-for-combphy-on-rk3568.patch
new file mode 100644
index 0000000000..32849564de
--- /dev/null
+++
b/target/linux/rockchip/patches-6.6/035-v6.13-arm64-dts-rockchip-add-reset-names-for-combphy-on-rk3568.patch
@@ -0,0 +1,44 @@
+From 8b9c12757f919157752646faf3821abf2b7d2a64 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amad...@jmu.edu.cn>
+Date: Fri, 22 Nov 2024 15:30:05 +0800
+Subject: [PATCH] arm64: dts: rockchip: add reset-names for combphy on rk3568
+
+The reset-names of combphy are missing, add it.
+
+Signed-off-by: Chukun Pan <amad...@jmu.edu.cn>
+Fixes: fd3ac6e80497 ("dt-bindings: phy: rockchip: rk3588 has two reset lines")
+Link: https://lore.kernel.org/r/20241122073006.99309-1-amad...@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <he...@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 1 +
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
+ 2 files changed, 3 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -223,6 +223,7 @@
+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY0>;
++ reset-names = "phy";
+ rockchip,pipe-grf = <&pipegrf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+ #phy-cells = <1>;
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1747,6 +1747,7 @@
+ assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY1>;
++ reset-names = "phy";
+ rockchip,pipe-grf = <&pipegrf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
+ #phy-cells = <1>;
+@@ -1763,6 +1764,7 @@
+ assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY2>;
++ reset-names = "phy";
+ rockchip,pipe-grf = <&pipegrf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
+ #phy-cells = <1>;
--
2.25.1
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