Once upon a time, Luiz Angelo Daros de Luca <[email protected]> wrote:
>
> Hi Andrey,
>
> > It simple a) don't apply to master tree; b) not working - MAX_RX_LENGTH
> > constant not
> > touched, GSW_REG_GMACCR not tweaked for accepting jumbo frames.
>
> a) Sorry, I missed your answer and thanks for the review. Yes, it was
> not applying to master. It was based on another patch deeper in my
> tree. I fixed that a long time ago but I postponed the fix as I didn't
> see any interest from ML (I was wrong). I was focusing on upstream
> patches (realtek dsa switches merged into 5.18) and postponed the
> ramips fixes for when they would be needed.
>
> b) MAX_RX_LENGTH seems to be used only for keeping the buffer at least
> over (MAX_RX_LENGTH - FE_RX_ETH_HLEN) and it does not care when mtu is
> actually even bigger than (MAX_RX_LENGTH - FE_RX_ETH_HLEN). See:
MAX_RX_LENGTH affects buffers for DMA transfers.
> target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c:
> static inline int fe_max_frag_size(int mtu)
> {
> /* make sure buf_size will be at least MAX_RX_LENGTH */
> if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
> mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
>
> return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
> SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
> }
>
> static inline int fe_max_buf_size(int frag_size)
> {
> int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
> SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
>
> BUG_ON(buf_size < MAX_RX_LENGTH);
> return buf_size;
> }
>
> Does this logic need to be updated somehow for jumbo or even non jumbo frames?
No. Only maybe remove BUG_ON().
> c) MAX_RX_JUMBO and MAX_RX_PKT_LEN in GSW_REG_GMACCR are switch regs
> while I touched only ethernet frame engine regs.
There are two parts - FE and switch. And both need to be properly programmed.
> For me, the switch was happily forwarding frames with 8 extra bytes (DSA
> tag). In my
> device, the internal switch was being used as a transparent switch (no
> vlan), connecting to an external switch (RTL8367S) through the RGMII
> interface. Maybe the small increase was still falling into an accepted
> frame size range (for the switch), the RGMII interface might have a
> less restricted access or disabling vlans also makes the switch more
> tolerant to larger frames. The FastEthernet ports are not used in my
> device so extra bytes might need to come from the RTL8367S DSA switch,
> which currently does not support increasing the MTU of slave ports. I
> cannot easily generate incoming frames larger than 1508.
I have hardware with an internal switch. And your patch is not working for it.
> I wonder if it is the ethernet driver's responsibility to increase the
> switch frame size or if it is the switch driver (swconfig or DSA). It
> might not only affect the CPU port but any traffic between ports. I'm
> not very comfortable touching a piece of code I cannot really test. If
> a dev does have access to a mt7620 device that actually uses its
> ports, it might be easier for that dev to go ahead and fix it himself.
> The patch is as simple as:
>
> #ifdef CONFIG_SOC_MT7620
> if (<frame size calculated from mtu> > 1536) {
> // set MAX_RX_JUMBO as 2k
> GSW_REG_GMACCR |= 0x2 << 2
> // set MAX_RX_PKT_LEN as MAX_RX_JUMBO
> GSW_REG_GMACCR |= 0x3
> }
> #endif
> It might be inserted into the same place fe_max_frag_size is called in
> fe_change_mtu() but I'm not sure how it would interact with other non
> MT7621 SoCs.
> I wonder why MT7621 does not seem to bother the extra bytes. Anyway,
> the patch is a step further and it is still required and enough for an
> external DSA switch.
> The extra GSW_REG_GMACCR tweaks, if needed, might be added in the
> future. I'll wait a couple of days to settle this thread and resubmit
> a master-compatible v2 (just a minor fix you pointed out) with an
> extra patch for disabling checksum offload when the DSA tag is not
> Mediatek.
Attached patch tested on real MT7620 with internal switch and it is
able to operate with a 2048-bytes frame (included single VLAN tag).
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c
@@ -42,7 +42,14 @@
#include "mdio.h"
#include "ethtool.h"
+#if defined(CONFIG_SOC_MT7620)
+#define DMA_FWD_REG MT7620A_GDMA1_FWD_CFG
+#define MAX_RX_LENGTH 2048
+#else
+#define DMA_FWD_REG FE_GDMA1_FWD_CFG
#define MAX_RX_LENGTH 1536
+#endif
+
#define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
#define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
#define DMA_DUMMY_DESC 0xffffffff
@@ -1182,7 +1165,7 @@ void fe_fwd_config(struct fe_priv *priv)
{
u32 fwd_cfg;
- fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
+ fwd_cfg = fe_r32(DMA_FWD_REG);
/* disable jumbo frame */
if (priv->flags & FE_FLAG_JUMBO_FRAME)
@@ -1191,19 +1174,19 @@ void fe_fwd_config(struct fe_priv *priv)
/* set unicast/multicast/broadcast frame to cpu */
fwd_cfg &= ~0xffff;
- fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
+ fe_w32(fwd_cfg, DMA_FWD_REG);
}
static void fe_rxcsum_config(bool enable)
{
if (enable)
- fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
+ fe_w32(fe_r32(DMA_FWD_REG) | (FE_GDM1_ICS_EN |
FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
- FE_GDMA1_FWD_CFG);
+ DMA_FWD_REG);
else
- fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
+ fe_w32(fe_r32(DMA_FWD_REG) & ~(FE_GDM1_ICS_EN |
FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
- FE_GDMA1_FWD_CFG);
+ DMA_FWD_REG);
}
static void fe_txcsum_config(bool enable)
@@ -1482,7 +1465,7 @@ static int fe_change_mtu(struct net_devi
fe_stop(dev);
if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
- fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
+ fwd_cfg = fe_r32(DMA_FWD_REG);
if (new_mtu <= ETH_DATA_LEN) {
fwd_cfg &= ~FE_GDM1_JMB_EN;
} else {
@@ -1491,7 +1474,7 @@ static int fe_change_mtu(struct net_devi
fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
}
- fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
+ fe_w32(fwd_cfg, DMA_FWD_REG);
}
return fe_open(dev);
@@ -1608,7 +1591,7 @@ static int fe_probe(struct platform_devi
NETIF_F_HW_VLAN_CTAG_RX);
netdev->features |= netdev->hw_features;
- if (IS_ENABLED(CONFIG_SOC_MT7621))
+ if (IS_ENABLED(CONFIG_SOC_MT7620))
netdev->max_mtu = 2048;
/* fake rx vlan filter func. to support tx vlan offload func */
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
@@ -345,7 +345,8 @@ static void mt7620_init_data(struct fe_s
struct fe_priv *priv = netdev_priv(netdev);
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
- FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;
+ FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH |
+ FE_FLAG_JUMBO_FRAME;
netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
NETIF_F_HW_VLAN_CTAG_TX;
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
@@ -161,9 +161,15 @@ static void mt7620_hw_init(struct mt7620
/* CPU Port6 Force Link 1G, FC ON */
mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
- /* Set Port 6 as CPU Port */
+ /* ARL_MAC_FCR: Set Port 6 as CPU Port */
mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
+ val = mtk_switch_r32(gsw, GSW_REG_GMACCR);
+ val &= ~(GMACCR_JMB_LEN_MASK << GMACCR_JMB_LEN_SHIFT);
+ /* Set 2k max frime size and enable MAX_RX_JUMBO */
+ val |= (2 << GMACCR_JMB_LEN_SHIFT) | GMACCR_JMB_ENABLE;
+ mtk_switch_w32(gsw, val, GSW_REG_GMACCR);
+
/* setup port 4 */
if (gsw->port4_ephy) {
val = rt_sysc_r32(SYSC_REG_CFG1);
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.h
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.h
@@ -35,6 +35,13 @@
#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
+// Global MAC control register
+#define GSW_REG_GMACCR 0x3FE0
+#define GMACCR_JMB_LEN_MASK 0x0F
+#define GMACCR_JMB_LEN_SHIFT 2
+// MAX_RX_PKT_LEN bits 0:1
+#define GMACCR_JMB_ENABLE 0x2
+
#define GSW_REG_SMACCR0 0x3fE4
#define GSW_REG_SMACCR1 0x3fE8
#define GSW_REG_CKGCR 0x3ff0
@@ -50,9 +57,6 @@
#define GSW_REG_MAC_P0_MCR 0x100
#define GSW_REG_MAC_P1_MCR 0x200
-// Global MAC control register
-#define GSW_REG_GMACCR 0x30E0
-
#define SYSC_REG_CHIP_REV_ID 0x0c
#define SYSC_REG_CFG1 0x14
#define PCIE_RC_MODE BIT(8)
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