From: Ian Chang <ianch...@ieiworld.com>
Signed-off-by: Ian Chang <ianch...@ieiworld.com>
---
...l-Add-support-for-Marvell-CN9130-SoC.patch | 60 +
...64-dts-marvell-Add-support-for-CP115.patch | 35 +
...ll-Prepare-the-introduction-of-CP115.patch | 1331 +++++++++++++++++
...ell-Add-support-for-AP807-AP807-quad.patch | 110 ++
...ell-Add-AP807-quad-cache-description.patch | 91 ++
...l-Drop-PCIe-I-O-ranges-from-CP11x-fi.patch | 145 ++
...l-Externalize-PCIe-macros-from-CP11x.patch | 137 ++
7 files changed, 1909 insertions(+)
create mode 100644
target/linux/mvebu/patches-5.4/000-v5.5-arm64-dts-marvell-Add-support-for-Marvell-CN9130-SoC.patch
create mode 100644
target/linux/mvebu/patches-5.4/001-v5.5-arm64-dts-marvell-Add-support-for-CP115.patch
create mode 100644
target/linux/mvebu/patches-5.4/002-v5.5-arm64-dts-marvell-Prepare-the-introduction-of-CP115.patch
create mode 100644
target/linux/mvebu/patches-5.4/003-v5.5-arm64-dts-marvell-Add-support-for-AP807-AP807-quad.patch
create mode 100644
target/linux/mvebu/patches-5.4/004-v5.5-arm64-dts-marvell-Add-AP807-quad-cache-description.patch
create mode 100644
target/linux/mvebu/patches-5.4/005-v5.5-arm64-dts-marvell-Drop-PCIe-I-O-ranges-from-CP11x-fi.patch
create mode 100644
target/linux/mvebu/patches-5.4/006-v5.5-arm64-dts-marvell-Externalize-PCIe-macros-from-CP11x.patch
diff --git
a/target/linux/mvebu/patches-5.4/000-v5.5-arm64-dts-marvell-Add-support-for-Marvell-CN9130-SoC.patch
b/target/linux/mvebu/patches-5.4/000-v5.5-arm64-dts-marvell-Add-support-for-Marvell-CN9130-SoC.patch
new file mode 100644
index 0000000000..d5e5d6e0b2
--- /dev/null
+++
b/target/linux/mvebu/patches-5.4/000-v5.5-arm64-dts-marvell-Add-support-for-Marvell-CN9130-SoC.patch
@@ -0,0 +1,60 @@
+From 6b8970bd8d7a17a648e31f3996d9b21336b4a2cf Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.ray...@bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:35 +0200
+Subject: [PATCH] arm64: dts: marvell: Add support for Marvell CN9130 SoC
+ support
+
+A CN9130 SoC has one AP807 and one internal CP115.
+
+Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/cn9130.dtsi | 37 +++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/marvell/cn9130.dtsi
+
+diff --git a/arch/arm64/boot/dts/marvell/cn9130.dtsi
b/arch/arm64/boot/dts/marvell/cn9130.dtsi
+new file mode 100644
+index 000000000000..a2b7e5ec979d
+--- /dev/null
++++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi
+@@ -0,0 +1,37 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 Marvell International Ltd.
++ *
++ * Device tree for the CN9130 SoC.
++ */
++
++#include "armada-ap807-quad.dtsi"
++
++/ {
++ model = "Marvell Armada CN9130 SoC";
++ compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
++ "marvell,armada-ap807";
++};
++
++/*
++ * Instantiate the internal CP115
++ */
++
++#define CP11X_NAME cp0
++#define CP11X_BASE f2000000
++#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
++ 0xe0000000 + ((iface - 1) *
0x1000000))
++#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
++#define CP11X_PCIE0_BASE f2600000
++#define CP11X_PCIE1_BASE f2620000
++#define CP11X_PCIE2_BASE f2640000
++
++#include "armada-cp115.dtsi"
++
++#undef CP11X_NAME
++#undef CP11X_BASE
++#undef CP11X_PCIEx_MEM_BASE
++#undef CP11X_PCIEx_MEM_SIZE
++#undef CP11X_PCIE0_BASE
++#undef CP11X_PCIE1_BASE
++#undef CP11X_PCIE2_BASE
+--
+2.17.1
diff --git
a/target/linux/mvebu/patches-5.4/001-v5.5-arm64-dts-marvell-Add-support-for-CP115.patch
b/target/linux/mvebu/patches-5.4/001-v5.5-arm64-dts-marvell-Add-support-for-CP115.patch
new file mode 100644
index 0000000000..85395a358f
--- /dev/null
+++
b/target/linux/mvebu/patches-5.4/001-v5.5-arm64-dts-marvell-Add-support-for-CP115.patch
@@ -0,0 +1,35 @@
+From 96bb4b31aa660e39fca2bb464b9a9f399bd5b71c Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.ray...@bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:32 +0200
+Subject: [PATCH] arm64: dts: marvell: Add support for CP115
+
+Create a DTSI file based on the CP11x one. Differences will be
+described in the near future.
+
+Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/armada-cp115.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/marvell/armada-cp115.dtsi
+
+diff --git a/arch/arm64/boot/dts/marvell/armada-cp115.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp115.dtsi
+new file mode 100644
+index 000000000000..1d0a9653e681
+--- /dev/null
++++ b/arch/arm64/boot/dts/marvell/armada-cp115.dtsi
+@@ -0,0 +1,12 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 Marvell Technology Group Ltd.
++ *
++ * Device Tree file for Marvell Armada CP115.
++ */
++
++#define CP11X_TYPE cp115
++
++#include "armada-cp11x.dtsi"
++
++#undef CP11X_TYPE
+--
+2.17.1
diff --git
a/target/linux/mvebu/patches-5.4/002-v5.5-arm64-dts-marvell-Prepare-the-introduction-of-CP115.patch
b/target/linux/mvebu/patches-5.4/002-v5.5-arm64-dts-marvell-Prepare-the-introduction-of-CP115.patch
new file mode 100644
index 0000000000..9190bec710
--- /dev/null
+++
b/target/linux/mvebu/patches-5.4/002-v5.5-arm64-dts-marvell-Prepare-the-introduction-of-CP115.patch
@@ -0,0 +1,1331 @@
+From 47cf40af64c35a69ef6a193c47768ad1bda29db2 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.ray...@bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:29 +0200
+Subject: [PATCH] arm64: dts: marvell: Prepare the introduction of CP115
+
+CP110 and CP115 are almost the same in terms of features and have a
+very limited set of differences. Let's create an armada-cp11x.dtsi
+file which will be used to instantiate both CP110 and CP115
+nodes.
+
+The only changes between the two armada-cp11{0,x}.dtsi files are the
+following naming in macros: s/CP110/CP11X/.
+
+Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 28 +-
+ arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 56 +-
+ .../arm64/boot/dts/marvell/armada-common.dtsi | 4 +-
+ arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 575 +----------------
+ arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 579 ++++++++++++++++++
+ 5 files changed, 627 insertions(+), 615 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+
+diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+index e5c6d7c25819..4e78ccd207b7 100644
+--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+@@ -17,23 +17,23 @@
+ /*
+ * Instantiate the CP110
+ */
+-#define CP110_NAME cp0
+-#define CP110_BASE f2000000
+-#define CP110_PCIE_IO_BASE 0xf9000000
+-#define CP110_PCIE_MEM_BASE 0xf6000000
+-#define CP110_PCIE0_BASE f2600000
+-#define CP110_PCIE1_BASE f2620000
+-#define CP110_PCIE2_BASE f2640000
++#define CP11X_NAME cp0
++#define CP11X_BASE f2000000
++#define CP11X_PCIE_IO_BASE 0xf9000000
++#define CP11X_PCIE_MEM_BASE 0xf6000000
++#define CP11X_PCIE0_BASE f2600000
++#define CP11X_PCIE1_BASE f2620000
++#define CP11X_PCIE2_BASE f2640000
+
+ #include "armada-cp110.dtsi"
+
+-#undef CP110_NAME
+-#undef CP110_BASE
+-#undef CP110_PCIE_IO_BASE
+-#undef CP110_PCIE_MEM_BASE
+-#undef CP110_PCIE0_BASE
+-#undef CP110_PCIE1_BASE
+-#undef CP110_PCIE2_BASE
++#undef CP11X_NAME
++#undef CP11X_BASE
++#undef CP11X_PCIE_IO_BASE
++#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIE0_BASE
++#undef CP11X_PCIE1_BASE
++#undef CP11X_PCIE2_BASE
+
+ &cp0_gpio1 {
+ status = "okay";
+diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+index 8129b40f12a4..ebb98836ec9c 100644
+--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+@@ -19,44 +19,44 @@
+ /*
+ * Instantiate the master CP110
+ */
+-#define CP110_NAME cp0
+-#define CP110_BASE f2000000
+-#define CP110_PCIE_IO_BASE 0xf9000000
+-#define CP110_PCIE_MEM_BASE 0xf6000000
+-#define CP110_PCIE0_BASE f2600000
+-#define CP110_PCIE1_BASE f2620000
+-#define CP110_PCIE2_BASE f2640000
++#define CP11X_NAME cp0
++#define CP11X_BASE f2000000
++#define CP11X_PCIE_IO_BASE 0xf9000000
++#define CP11X_PCIE_MEM_BASE 0xf6000000
++#define CP11X_PCIE0_BASE f2600000
++#define CP11X_PCIE1_BASE f2620000
++#define CP11X_PCIE2_BASE f2640000
+
+ #include "armada-cp110.dtsi"
+
+-#undef CP110_NAME
+-#undef CP110_BASE
+-#undef CP110_PCIE_IO_BASE
+-#undef CP110_PCIE_MEM_BASE
+-#undef CP110_PCIE0_BASE
+-#undef CP110_PCIE1_BASE
+-#undef CP110_PCIE2_BASE
++#undef CP11X_NAME
++#undef CP11X_BASE
++#undef CP11X_PCIE_IO_BASE
++#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIE0_BASE
++#undef CP11X_PCIE1_BASE
++#undef CP11X_PCIE2_BASE
+
+ /*
+ * Instantiate the slave CP110
+ */
+-#define CP110_NAME cp1
+-#define CP110_BASE f4000000
+-#define CP110_PCIE_IO_BASE 0xfd000000
+-#define CP110_PCIE_MEM_BASE 0xfa000000
+-#define CP110_PCIE0_BASE f4600000
+-#define CP110_PCIE1_BASE f4620000
+-#define CP110_PCIE2_BASE f4640000
++#define CP11X_NAME cp1
++#define CP11X_BASE f4000000
++#define CP11X_PCIE_IO_BASE 0xfd000000
++#define CP11X_PCIE_MEM_BASE 0xfa000000
++#define CP11X_PCIE0_BASE f4600000
++#define CP11X_PCIE1_BASE f4620000
++#define CP11X_PCIE2_BASE f4640000
+
+ #include "armada-cp110.dtsi"
+
+-#undef CP110_NAME
+-#undef CP110_BASE
+-#undef CP110_PCIE_IO_BASE
+-#undef CP110_PCIE_MEM_BASE
+-#undef CP110_PCIE0_BASE
+-#undef CP110_PCIE1_BASE
+-#undef CP110_PCIE2_BASE
++#undef CP11X_NAME
++#undef CP11X_BASE
++#undef CP11X_PCIE_IO_BASE
++#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIE0_BASE
++#undef CP11X_PCIE1_BASE
++#undef CP11X_PCIE2_BASE
+
+ /* The 80x0 has two CP blocks, but uses only one block from each. */
+ &cp1_gpio1 {
+diff --git a/arch/arm64/boot/dts/marvell/armada-common.dtsi
b/arch/arm64/boot/dts/marvell/armada-common.dtsi
+index b29c6405d214..c04c6c475022 100644
+--- a/arch/arm64/boot/dts/marvell/armada-common.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-common.dtsi
+@@ -6,6 +6,6 @@
+ /* Common definitions used by Armada 7K/8K DTs */
+ #define PASTER(x, y) x ## y
+ #define EVALUATOR(x, y) PASTER(x, y)
+-#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
+-#define CP110_NODE_NAME(name) EVALUATOR(CP110_NAME, EVALUATOR(-, name))
++#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))
++#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))
+ #define ADDRESSIFY(addr) EVALUATOR(0x, addr)
+diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+index 8259fc8f86f2..4fd33b0fa56e 100644
+--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+@@ -1,579 +1,12 @@
+ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+- * Copyright (C) 2016 Marvell Technology Group Ltd.
++ * Copyright (C) 2019 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada CP110.
+ */
+
+-#include <dt-bindings/interrupt-controller/mvebu-icu.h>
+-#include <dt-bindings/thermal/thermal.h>
++#define CP11X_TYPE cp110
+
+-#include "armada-common.dtsi"
++#include "armada-cp11x.dtsi"
+
+-#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface *
0x10000))
+-#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface *
0x1000000))
+-#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
+-
+-/ {
+- /*
+- * The contents of the node are defined below, in order to
+- * save one indentation level
+- */
+- CP110_NAME: CP110_NAME { };
+-
+- /*
+- * CPs only have one sensor in the thermal IC.
+- *
+- * The cooling maps are empty as there are no cooling devices.
+- */
+- thermal-zones {
+- CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
+- polling-delay-passive = <0>; /* Interrupt driven */
+- polling-delay = <0>; /* Interrupt driven */
+-
+- thermal-sensors = <&CP110_LABEL(thermal) 0>;
+-
+- trips {
+- CP110_LABEL(crit): crit {
+- temperature = <100000>; /* mC degrees */
+- hysteresis = <2000>; /* mC degrees */
+- type = "critical";
+- };
+- };
+-
+- cooling-maps { };
+- };
+- };
+-};
+-
+-&CP110_NAME {
+- #address-cells = <2>;
+- #size-cells = <2>;
+- compatible = "simple-bus";
+- interrupt-parent = <&CP110_LABEL(icu_nsr)>;
+- ranges;
+-
+- config-space@CP110_BASE {
+- #address-cells = <1>;
+- #size-cells = <1>;
+- compatible = "simple-bus";
+- ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
+-
+- CP110_LABEL(ethernet): ethernet@0 {
+- compatible = "marvell,armada-7k-pp22";
+- reg = <0x0 0x100000>, <0x129000 0xb000>;
+- clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1
9>,
+- <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1
6>,
+- <&CP110_LABEL(clk) 1 18>;
+- clock-names = "pp_clk", "gop_clk",
+- "mg_clk", "mg_core_clk", "axi_clk";
+- marvell,system-controller = <&CP110_LABEL(syscon0)>;
+- status = "disabled";
+- dma-coherent;
+-
+- CP110_LABEL(eth0): eth0 {
+- interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
+- <43 IRQ_TYPE_LEVEL_HIGH>,
+- <47 IRQ_TYPE_LEVEL_HIGH>,
+- <51 IRQ_TYPE_LEVEL_HIGH>,
+- <55 IRQ_TYPE_LEVEL_HIGH>,
+- <59 IRQ_TYPE_LEVEL_HIGH>,
+- <63 IRQ_TYPE_LEVEL_HIGH>,
+- <67 IRQ_TYPE_LEVEL_HIGH>,
+- <71 IRQ_TYPE_LEVEL_HIGH>,
+- <129 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "hif0", "hif1", "hif2",
+- "hif3", "hif4", "hif5", "hif6", "hif7",
+- "hif8", "link";
+- port-id = <0>;
+- gop-port-id = <0>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(eth1): eth1 {
+- interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
+- <44 IRQ_TYPE_LEVEL_HIGH>,
+- <48 IRQ_TYPE_LEVEL_HIGH>,
+- <52 IRQ_TYPE_LEVEL_HIGH>,
+- <56 IRQ_TYPE_LEVEL_HIGH>,
+- <60 IRQ_TYPE_LEVEL_HIGH>,
+- <64 IRQ_TYPE_LEVEL_HIGH>,
+- <68 IRQ_TYPE_LEVEL_HIGH>,
+- <72 IRQ_TYPE_LEVEL_HIGH>,
+- <128 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "hif0", "hif1", "hif2",
+- "hif3", "hif4", "hif5", "hif6", "hif7",
+- "hif8", "link";
+- port-id = <1>;
+- gop-port-id = <2>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(eth2): eth2 {
+- interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
+- <45 IRQ_TYPE_LEVEL_HIGH>,
+- <49 IRQ_TYPE_LEVEL_HIGH>,
+- <53 IRQ_TYPE_LEVEL_HIGH>,
+- <57 IRQ_TYPE_LEVEL_HIGH>,
+- <61 IRQ_TYPE_LEVEL_HIGH>,
+- <65 IRQ_TYPE_LEVEL_HIGH>,
+- <69 IRQ_TYPE_LEVEL_HIGH>,
+- <73 IRQ_TYPE_LEVEL_HIGH>,
+- <127 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "hif0", "hif1", "hif2",
+- "hif3", "hif4", "hif5", "hif6", "hif7",
+- "hif8", "link";
+- port-id = <2>;
+- gop-port-id = <3>;
+- status = "disabled";
+- };
+- };
+-
+- CP110_LABEL(comphy): phy@120000 {
+- compatible = "marvell,comphy-cp110";
+- reg = <0x120000 0x6000>;
+- marvell,system-controller = <&CP110_LABEL(syscon0)>;
+- clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1
6>,
+- <&CP110_LABEL(clk) 1 18>;
+- clock-names = "mg_clk", "mg_core_clk", "axi_clk";
+- #address-cells = <1>;
+- #size-cells = <0>;
+-
+- CP110_LABEL(comphy0): phy@0 {
+- reg = <0>;
+- #phy-cells = <1>;
+- };
+-
+- CP110_LABEL(comphy1): phy@1 {
+- reg = <1>;
+- #phy-cells = <1>;
+- };
+-
+- CP110_LABEL(comphy2): phy@2 {
+- reg = <2>;
+- #phy-cells = <1>;
+- };
+-
+- CP110_LABEL(comphy3): phy@3 {
+- reg = <3>;
+- #phy-cells = <1>;
+- };
+-
+- CP110_LABEL(comphy4): phy@4 {
+- reg = <4>;
+- #phy-cells = <1>;
+- };
+-
+- CP110_LABEL(comphy5): phy@5 {
+- reg = <5>;
+- #phy-cells = <1>;
+- };
+- };
+-
+- CP110_LABEL(mdio): mdio@12a200 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "marvell,orion-mdio";
+- reg = <0x12a200 0x10>;
+- clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1
5>,
+- <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1
18>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(xmdio): mdio@12a600 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "marvell,xmdio";
+- reg = <0x12a600 0x10>;
+- clocks = <&CP110_LABEL(clk) 1 5>,
+- <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1
18>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(icu): interrupt-controller@1e0000 {
+- compatible = "marvell,cp110-icu";
+- reg = <0x1e0000 0x440>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+-
+- CP110_LABEL(icu_nsr): interrupt-controller@10 {
+- compatible = "marvell,cp110-icu-nsr";
+- reg = <0x10 0x20>;
+- #interrupt-cells = <2>;
+- interrupt-controller;
+- msi-parent = <&gicp>;
+- };
+-
+- CP110_LABEL(icu_sei): interrupt-controller@50 {
+- compatible = "marvell,cp110-icu-sei";
+- reg = <0x50 0x10>;
+- #interrupt-cells = <2>;
+- interrupt-controller;
+- msi-parent = <&sei>;
+- };
+- };
+-
+- CP110_LABEL(rtc): rtc@284000 {
+- compatible = "marvell,armada-8k-rtc";
+- reg = <0x284000 0x20>, <0x284080 0x24>;
+- reg-names = "rtc", "rtc-soc";
+- interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
+- };
+-
+- CP110_LABEL(syscon0): system-controller@440000 {
+- compatible = "syscon", "simple-mfd";
+- reg = <0x440000 0x2000>;
+-
+- CP110_LABEL(clk): clock {
+- compatible = "marvell,cp110-clock";
+- #clock-cells = <2>;
+- };
+-
+- CP110_LABEL(gpio1): gpio@100 {
+- compatible = "marvell,armada-8k-gpio";
+- offset = <0x100>;
+- ngpios = <32>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
+- interrupt-controller;
+- interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
+- <85 IRQ_TYPE_LEVEL_HIGH>,
+- <84 IRQ_TYPE_LEVEL_HIGH>,
+- <83 IRQ_TYPE_LEVEL_HIGH>;
+- #interrupt-cells = <2>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(gpio2): gpio@140 {
+- compatible = "marvell,armada-8k-gpio";
+- offset = <0x140>;
+- ngpios = <31>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
+- interrupt-controller;
+- interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
+- <81 IRQ_TYPE_LEVEL_HIGH>,
+- <80 IRQ_TYPE_LEVEL_HIGH>,
+- <79 IRQ_TYPE_LEVEL_HIGH>;
+- #interrupt-cells = <2>;
+- status = "disabled";
+- };
+- };
+-
+- CP110_LABEL(syscon1): system-controller@400000 {
+- compatible = "syscon", "simple-mfd";
+- reg = <0x400000 0x1000>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+-
+- CP110_LABEL(thermal): thermal-sensor@70 {
+- compatible = "marvell,armada-cp110-thermal";
+- reg = <0x70 0x10>;
+- interrupts-extended =
+- <&CP110_LABEL(icu_sei) 116
IRQ_TYPE_LEVEL_HIGH>;
+- #thermal-sensor-cells = <1>;
+- };
+- };
+-
+- CP110_LABEL(usb3_0): usb3@500000 {
+- compatible = "marvell,armada-8k-xhci",
+- "generic-xhci";
+- reg = <0x500000 0x4000>;
+- dma-coherent;
+- interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 22>,
+- <&CP110_LABEL(clk) 1 16>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(usb3_1): usb3@510000 {
+- compatible = "marvell,armada-8k-xhci",
+- "generic-xhci";
+- reg = <0x510000 0x4000>;
+- dma-coherent;
+- interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 23>,
+- <&CP110_LABEL(clk) 1 16>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(sata0): sata@540000 {
+- compatible = "marvell,armada-8k-ahci",
+- "generic-ahci";
+- reg = <0x540000 0x30000>;
+- dma-coherent;
+- interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&CP110_LABEL(clk) 1 15>,
+- <&CP110_LABEL(clk) 1 16>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- status = "disabled";
+-
+- sata-port@0 {
+- reg = <0>;
+- };
+-
+- sata-port@1 {
+- reg = <1>;
+- };
+- };
+-
+- CP110_LABEL(xor0): xor@6a0000 {
+- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+- reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
+- dma-coherent;
+- msi-parent = <&gic_v2m0>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 8>,
+- <&CP110_LABEL(clk) 1 14>;
+- };
+-
+- CP110_LABEL(xor1): xor@6c0000 {
+- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+- reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
+- dma-coherent;
+- msi-parent = <&gic_v2m0>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 7>,
+- <&CP110_LABEL(clk) 1 14>;
+- };
+-
+- CP110_LABEL(spi0): spi@700600 {
+- compatible = "marvell,armada-380-spi";
+- reg = <0x700600 0x50>;
+- #address-cells = <0x1>;
+- #size-cells = <0x0>;
+- clock-names = "core", "axi";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(spi1): spi@700680 {
+- compatible = "marvell,armada-380-spi";
+- reg = <0x700680 0x50>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clock-names = "core", "axi";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(i2c0): i2c@701000 {
+- compatible = "marvell,mv78230-i2c";
+- reg = <0x701000 0x20>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(i2c1): i2c@701100 {
+- compatible = "marvell,mv78230-i2c";
+- reg = <0x701100 0x20>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(uart0): serial@702000 {
+- compatible = "snps,dw-apb-uart";
+- reg = <0x702000 0x100>;
+- reg-shift = <2>;
+- interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
+- reg-io-width = <1>;
+- clock-names = "baudclk", "apb_pclk";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(uart1): serial@702100 {
+- compatible = "snps,dw-apb-uart";
+- reg = <0x702100 0x100>;
+- reg-shift = <2>;
+- interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
+- reg-io-width = <1>;
+- clock-names = "baudclk", "apb_pclk";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(uart2): serial@702200 {
+- compatible = "snps,dw-apb-uart";
+- reg = <0x702200 0x100>;
+- reg-shift = <2>;
+- interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
+- reg-io-width = <1>;
+- clock-names = "baudclk", "apb_pclk";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(uart3): serial@702300 {
+- compatible = "snps,dw-apb-uart";
+- reg = <0x702300 0x100>;
+- reg-shift = <2>;
+- interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
+- reg-io-width = <1>;
+- clock-names = "baudclk", "apb_pclk";
+- clocks = <&CP110_LABEL(clk) 1 21>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(nand_controller): nand@720000 {
+- /*
+- * Due to the limitation of the pins available
+- * this controller is only usable on the CPM
+- * for A7K and on the CPS for A8K.
+- */
+- compatible = "marvell,armada-8k-nand-controller",
+- "marvell,armada370-nand-controller";
+- reg = <0x720000 0x54>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 2>,
+- <&CP110_LABEL(clk) 1 17>;
+- marvell,system-controller = <&CP110_LABEL(syscon0)>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(trng): trng@760000 {
+- compatible = "marvell,armada-8k-rng",
+- "inside-secure,safexcel-eip76";
+- reg = <0x760000 0x7d>;
+- interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 25>,
+- <&CP110_LABEL(clk) 1 17>;
+- status = "okay";
+- };
+-
+- CP110_LABEL(sdhci0): sdhci@780000 {
+- compatible = "marvell,armada-cp110-sdhci";
+- reg = <0x780000 0x300>;
+- interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+- clock-names = "core", "axi";
+- clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1
18>;
+- dma-coherent;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(crypto): crypto@800000 {
+- compatible = "inside-secure,safexcel-eip197b";
+- reg = <0x800000 0x200000>;
+- interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
+- <88 IRQ_TYPE_LEVEL_HIGH>,
+- <89 IRQ_TYPE_LEVEL_HIGH>,
+- <90 IRQ_TYPE_LEVEL_HIGH>,
+- <91 IRQ_TYPE_LEVEL_HIGH>,
+- <92 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "mem", "ring0", "ring1",
+- "ring2", "ring3", "eip";
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 26>,
+- <&CP110_LABEL(clk) 1 17>;
+- dma-coherent;
+- };
+- };
+-
+- CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
+- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+- reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
+- <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
+- reg-names = "ctrl", "config";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- #interrupt-cells = <1>;
+- device_type = "pci";
+- dma-coherent;
+- msi-parent = <&gic_v2m0>;
+-
+- bus-range = <0 0xff>;
+- ranges =
+- /* downstream I/O */
+- <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0)
0 0x10000
+- /* non-prefetchable memory */
+- 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0)
0 0xf00000>;
+- interrupt-map-mask = <0 0 0 0>;
+- interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22
IRQ_TYPE_LEVEL_HIGH>;
+- interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+- num-lanes = <1>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
+- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+- reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
+- <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
+- reg-names = "ctrl", "config";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- #interrupt-cells = <1>;
+- device_type = "pci";
+- dma-coherent;
+- msi-parent = <&gic_v2m0>;
+-
+- bus-range = <0 0xff>;
+- ranges =
+- /* downstream I/O */
+- <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1)
0 0x10000
+- /* non-prefetchable memory */
+- 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1)
0 0xf00000>;
+- interrupt-map-mask = <0 0 0 0>;
+- interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24
IRQ_TYPE_LEVEL_HIGH>;
+- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+-
+- num-lanes = <1>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
+- status = "disabled";
+- };
+-
+- CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
+- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+- reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
+- <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
+- reg-names = "ctrl", "config";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- #interrupt-cells = <1>;
+- device_type = "pci";
+- dma-coherent;
+- msi-parent = <&gic_v2m0>;
+-
+- bus-range = <0 0xff>;
+- ranges =
+- /* downstream I/O */
+- <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2)
0 0x10000
+- /* non-prefetchable memory */
+- 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2)
0 0xf00000>;
+- interrupt-map-mask = <0 0 0 0>;
+- interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23
IRQ_TYPE_LEVEL_HIGH>;
+- interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+-
+- num-lanes = <1>;
+- clock-names = "core", "reg";
+- clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
+- status = "disabled";
+- };
+-};
++#undef CP11X_TYPE
+diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+new file mode 100644
+index 000000000000..3e77cf34604c
+--- /dev/null
++++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+@@ -0,0 +1,579 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2016 Marvell Technology Group Ltd.
++ *
++ * Device Tree file for Marvell Armada CP11x.
++ */
++
++#include <dt-bindings/interrupt-controller/mvebu-icu.h>
++#include <dt-bindings/thermal/thermal.h>
++
++#include "armada-common.dtsi"
++
++#define CP11X_PCIEx_IO_BASE(iface) (CP11X_PCIE_IO_BASE + (iface *
0x10000))
++#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface *
0x1000000))
++#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
++
++/ {
++ /*
++ * The contents of the node are defined below, in order to
++ * save one indentation level
++ */
++ CP11X_NAME: CP11X_NAME { };
++
++ /*
++ * CPs only have one sensor in the thermal IC.
++ *
++ * The cooling maps are empty as there are no cooling devices.
++ */
++ thermal-zones {
++ CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
++ polling-delay-passive = <0>; /* Interrupt driven */
++ polling-delay = <0>; /* Interrupt driven */
++
++ thermal-sensors = <&CP11X_LABEL(thermal) 0>;
++
++ trips {
++ CP11X_LABEL(crit): crit {
++ temperature = <100000>; /* mC degrees */
++ hysteresis = <2000>; /* mC degrees */
++ type = "critical";
++ };
++ };
++
++ cooling-maps { };
++ };
++ };
++};
++
++&CP11X_NAME {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ compatible = "simple-bus";
++ interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
++ ranges;
++
++ config-space@CP11X_BASE {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "simple-bus";
++ ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
++
++ CP11X_LABEL(ethernet): ethernet@0 {
++ compatible = "marvell,armada-7k-pp22";
++ reg = <0x0 0x100000>, <0x129000 0xb000>;
++ clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1
9>,
++ <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1
6>,
++ <&CP11X_LABEL(clk) 1 18>;
++ clock-names = "pp_clk", "gop_clk",
++ "mg_clk", "mg_core_clk", "axi_clk";
++ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
++ status = "disabled";
++ dma-coherent;
++
++ CP11X_LABEL(eth0): eth0 {
++ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
++ <43 IRQ_TYPE_LEVEL_HIGH>,
++ <47 IRQ_TYPE_LEVEL_HIGH>,
++ <51 IRQ_TYPE_LEVEL_HIGH>,
++ <55 IRQ_TYPE_LEVEL_HIGH>,
++ <59 IRQ_TYPE_LEVEL_HIGH>,
++ <63 IRQ_TYPE_LEVEL_HIGH>,
++ <67 IRQ_TYPE_LEVEL_HIGH>,
++ <71 IRQ_TYPE_LEVEL_HIGH>,
++ <129 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "hif0", "hif1", "hif2",
++ "hif3", "hif4", "hif5", "hif6", "hif7",
++ "hif8", "link";
++ port-id = <0>;
++ gop-port-id = <0>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(eth1): eth1 {
++ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
++ <44 IRQ_TYPE_LEVEL_HIGH>,
++ <48 IRQ_TYPE_LEVEL_HIGH>,
++ <52 IRQ_TYPE_LEVEL_HIGH>,
++ <56 IRQ_TYPE_LEVEL_HIGH>,
++ <60 IRQ_TYPE_LEVEL_HIGH>,
++ <64 IRQ_TYPE_LEVEL_HIGH>,
++ <68 IRQ_TYPE_LEVEL_HIGH>,
++ <72 IRQ_TYPE_LEVEL_HIGH>,
++ <128 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "hif0", "hif1", "hif2",
++ "hif3", "hif4", "hif5", "hif6", "hif7",
++ "hif8", "link";
++ port-id = <1>;
++ gop-port-id = <2>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(eth2): eth2 {
++ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
++ <45 IRQ_TYPE_LEVEL_HIGH>,
++ <49 IRQ_TYPE_LEVEL_HIGH>,
++ <53 IRQ_TYPE_LEVEL_HIGH>,
++ <57 IRQ_TYPE_LEVEL_HIGH>,
++ <61 IRQ_TYPE_LEVEL_HIGH>,
++ <65 IRQ_TYPE_LEVEL_HIGH>,
++ <69 IRQ_TYPE_LEVEL_HIGH>,
++ <73 IRQ_TYPE_LEVEL_HIGH>,
++ <127 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "hif0", "hif1", "hif2",
++ "hif3", "hif4", "hif5", "hif6", "hif7",
++ "hif8", "link";
++ port-id = <2>;
++ gop-port-id = <3>;
++ status = "disabled";
++ };
++ };
++
++ CP11X_LABEL(comphy): phy@120000 {
++ compatible = "marvell,comphy-cp110";
++ reg = <0x120000 0x6000>;
++ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
++ clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1
6>,
++ <&CP11X_LABEL(clk) 1 18>;
++ clock-names = "mg_clk", "mg_core_clk", "axi_clk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ CP11X_LABEL(comphy0): phy@0 {
++ reg = <0>;
++ #phy-cells = <1>;
++ };
++
++ CP11X_LABEL(comphy1): phy@1 {
++ reg = <1>;
++ #phy-cells = <1>;
++ };
++
++ CP11X_LABEL(comphy2): phy@2 {
++ reg = <2>;
++ #phy-cells = <1>;
++ };
++
++ CP11X_LABEL(comphy3): phy@3 {
++ reg = <3>;
++ #phy-cells = <1>;
++ };
++
++ CP11X_LABEL(comphy4): phy@4 {
++ reg = <4>;
++ #phy-cells = <1>;
++ };
++
++ CP11X_LABEL(comphy5): phy@5 {
++ reg = <5>;
++ #phy-cells = <1>;
++ };
++ };
++
++ CP11X_LABEL(mdio): mdio@12a200 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "marvell,orion-mdio";
++ reg = <0x12a200 0x10>;
++ clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1
5>,
++ <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1
18>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(xmdio): mdio@12a600 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "marvell,xmdio";
++ reg = <0x12a600 0x10>;
++ clocks = <&CP11X_LABEL(clk) 1 5>,
++ <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1
18>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(icu): interrupt-controller@1e0000 {
++ compatible = "marvell,cp110-icu";
++ reg = <0x1e0000 0x440>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ CP11X_LABEL(icu_nsr): interrupt-controller@10 {
++ compatible = "marvell,cp110-icu-nsr";
++ reg = <0x10 0x20>;
++ #interrupt-cells = <2>;
++ interrupt-controller;
++ msi-parent = <&gicp>;
++ };
++
++ CP11X_LABEL(icu_sei): interrupt-controller@50 {
++ compatible = "marvell,cp110-icu-sei";
++ reg = <0x50 0x10>;
++ #interrupt-cells = <2>;
++ interrupt-controller;
++ msi-parent = <&sei>;
++ };
++ };
++
++ CP11X_LABEL(rtc): rtc@284000 {
++ compatible = "marvell,armada-8k-rtc";
++ reg = <0x284000 0x20>, <0x284080 0x24>;
++ reg-names = "rtc", "rtc-soc";
++ interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ CP11X_LABEL(syscon0): system-controller@440000 {
++ compatible = "syscon", "simple-mfd";
++ reg = <0x440000 0x2000>;
++
++ CP11X_LABEL(clk): clock {
++ compatible = "marvell,cp110-clock";
++ #clock-cells = <2>;
++ };
++
++ CP11X_LABEL(gpio1): gpio@100 {
++ compatible = "marvell,armada-8k-gpio";
++ offset = <0x100>;
++ ngpios = <32>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
++ interrupt-controller;
++ interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
++ <85 IRQ_TYPE_LEVEL_HIGH>,
++ <84 IRQ_TYPE_LEVEL_HIGH>,
++ <83 IRQ_TYPE_LEVEL_HIGH>;
++ #interrupt-cells = <2>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(gpio2): gpio@140 {
++ compatible = "marvell,armada-8k-gpio";
++ offset = <0x140>;
++ ngpios = <31>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
++ interrupt-controller;
++ interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
++ <81 IRQ_TYPE_LEVEL_HIGH>,
++ <80 IRQ_TYPE_LEVEL_HIGH>,
++ <79 IRQ_TYPE_LEVEL_HIGH>;
++ #interrupt-cells = <2>;
++ status = "disabled";
++ };
++ };
++
++ CP11X_LABEL(syscon1): system-controller@400000 {
++ compatible = "syscon", "simple-mfd";
++ reg = <0x400000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ CP11X_LABEL(thermal): thermal-sensor@70 {
++ compatible = "marvell,armada-cp110-thermal";
++ reg = <0x70 0x10>;
++ interrupts-extended =
++ <&CP11X_LABEL(icu_sei) 116
IRQ_TYPE_LEVEL_HIGH>;
++ #thermal-sensor-cells = <1>;
++ };
++ };
++
++ CP11X_LABEL(usb3_0): usb3@500000 {
++ compatible = "marvell,armada-8k-xhci",
++ "generic-xhci";
++ reg = <0x500000 0x4000>;
++ dma-coherent;
++ interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 22>,
++ <&CP11X_LABEL(clk) 1 16>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(usb3_1): usb3@510000 {
++ compatible = "marvell,armada-8k-xhci",
++ "generic-xhci";
++ reg = <0x510000 0x4000>;
++ dma-coherent;
++ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 23>,
++ <&CP11X_LABEL(clk) 1 16>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(sata0): sata@540000 {
++ compatible = "marvell,armada-8k-ahci",
++ "generic-ahci";
++ reg = <0x540000 0x30000>;
++ dma-coherent;
++ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&CP11X_LABEL(clk) 1 15>,
++ <&CP11X_LABEL(clk) 1 16>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ sata-port@0 {
++ reg = <0>;
++ };
++
++ sata-port@1 {
++ reg = <1>;
++ };
++ };
++
++ CP11X_LABEL(xor0): xor@6a0000 {
++ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
++ reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
++ dma-coherent;
++ msi-parent = <&gic_v2m0>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 8>,
++ <&CP11X_LABEL(clk) 1 14>;
++ };
++
++ CP11X_LABEL(xor1): xor@6c0000 {
++ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
++ reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
++ dma-coherent;
++ msi-parent = <&gic_v2m0>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 7>,
++ <&CP11X_LABEL(clk) 1 14>;
++ };
++
++ CP11X_LABEL(spi0): spi@700600 {
++ compatible = "marvell,armada-380-spi";
++ reg = <0x700600 0x50>;
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ clock-names = "core", "axi";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(spi1): spi@700680 {
++ compatible = "marvell,armada-380-spi";
++ reg = <0x700680 0x50>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clock-names = "core", "axi";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(i2c0): i2c@701000 {
++ compatible = "marvell,mv78230-i2c";
++ reg = <0x701000 0x20>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(i2c1): i2c@701100 {
++ compatible = "marvell,mv78230-i2c";
++ reg = <0x701100 0x20>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(uart0): serial@702000 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x702000 0x100>;
++ reg-shift = <2>;
++ interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <1>;
++ clock-names = "baudclk", "apb_pclk";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(uart1): serial@702100 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x702100 0x100>;
++ reg-shift = <2>;
++ interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <1>;
++ clock-names = "baudclk", "apb_pclk";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(uart2): serial@702200 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x702200 0x100>;
++ reg-shift = <2>;
++ interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <1>;
++ clock-names = "baudclk", "apb_pclk";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(uart3): serial@702300 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x702300 0x100>;
++ reg-shift = <2>;
++ interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <1>;
++ clock-names = "baudclk", "apb_pclk";
++ clocks = <&CP11X_LABEL(clk) 1 21>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(nand_controller): nand@720000 {
++ /*
++ * Due to the limitation of the pins available
++ * this controller is only usable on the CPM
++ * for A7K and on the CPS for A8K.
++ */
++ compatible = "marvell,armada-8k-nand-controller",
++ "marvell,armada370-nand-controller";
++ reg = <0x720000 0x54>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 2>,
++ <&CP11X_LABEL(clk) 1 17>;
++ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(trng): trng@760000 {
++ compatible = "marvell,armada-8k-rng",
++ "inside-secure,safexcel-eip76";
++ reg = <0x760000 0x7d>;
++ interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 25>,
++ <&CP11X_LABEL(clk) 1 17>;
++ status = "okay";
++ };
++
++ CP11X_LABEL(sdhci0): sdhci@780000 {
++ compatible = "marvell,armada-cp110-sdhci";
++ reg = <0x780000 0x300>;
++ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
++ clock-names = "core", "axi";
++ clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1
18>;
++ dma-coherent;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(crypto): crypto@800000 {
++ compatible = "inside-secure,safexcel-eip197b";
++ reg = <0x800000 0x200000>;
++ interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
++ <88 IRQ_TYPE_LEVEL_HIGH>,
++ <89 IRQ_TYPE_LEVEL_HIGH>,
++ <90 IRQ_TYPE_LEVEL_HIGH>,
++ <91 IRQ_TYPE_LEVEL_HIGH>,
++ <92 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "mem", "ring0", "ring1",
++ "ring2", "ring3", "eip";
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 26>,
++ <&CP11X_LABEL(clk) 1 17>;
++ dma-coherent;
++ };
++ };
++
++ CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
++ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
++ reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
++ <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
++ reg-names = "ctrl", "config";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ device_type = "pci";
++ dma-coherent;
++ msi-parent = <&gic_v2m0>;
++
++ bus-range = <0 0xff>;
++ ranges =
++ /* downstream I/O */
++ <0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0 CP11X_PCIEx_IO_BASE(0)
0 0x10000
++ /* non-prefetchable memory */
++ 0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0)
0 0xf00000>;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22
IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
++ num-lanes = <1>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
++ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
++ reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
++ <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
++ reg-names = "ctrl", "config";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ device_type = "pci";
++ dma-coherent;
++ msi-parent = <&gic_v2m0>;
++
++ bus-range = <0 0xff>;
++ ranges =
++ /* downstream I/O */
++ <0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0 CP11X_PCIEx_IO_BASE(1)
0 0x10000
++ /* non-prefetchable memory */
++ 0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1)
0 0xf00000>;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24
IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
++
++ num-lanes = <1>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
++ status = "disabled";
++ };
++
++ CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
++ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
++ reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
++ <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
++ reg-names = "ctrl", "config";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ device_type = "pci";
++ dma-coherent;
++ msi-parent = <&gic_v2m0>;
++
++ bus-range = <0 0xff>;
++ ranges =
++ /* downstream I/O */
++ <0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0 CP11X_PCIEx_IO_BASE(2)
0 0x10000
++ /* non-prefetchable memory */
++ 0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2)
0 0xf00000>;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23
IRQ_TYPE_LEVEL_HIGH>;
++ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
++
++ num-lanes = <1>;
++ clock-names = "core", "reg";
++ clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
++ status = "disabled";
++ };
++};
+--
+2.17.1
diff --git
a/target/linux/mvebu/patches-5.4/003-v5.5-arm64-dts-marvell-Add-support-for-AP807-AP807-quad.patch
b/target/linux/mvebu/patches-5.4/003-v5.5-arm64-dts-marvell-Add-support-for-AP807-AP807-quad.patch
new file mode 100644
index 0000000000..f90410a212
--- /dev/null
+++
b/target/linux/mvebu/patches-5.4/003-v5.5-arm64-dts-marvell-Add-support-for-AP807-AP807-quad.patch
@@ -0,0 +1,110 @@
+From cbafcad0641e99831ff7c57ac8f79aed502f33e5 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.ray...@bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:24 +0200
+Subject: [PATCH] arm64: dts: marvell: Add support for AP807/AP807-quad
+
+Describe AP807 and AP807-quad support.
+
+Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com>
+---
+ .../boot/dts/marvell/armada-ap807-quad.dtsi | 51 +++++++++++++++++++
+ arch/arm64/boot/dts/marvell/armada-ap807.dtsi | 29 +++++++++++
+ 2 files changed, 80 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+ create mode 100644 arch/arm64/boot/dts/marvell/armada-ap807.dtsi
+
+diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+new file mode 100644
+index 000000000000..65364691257d
+--- /dev/null
++++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+@@ -0,0 +1,51 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for Marvell Armada AP807 Quad
++ *
++ * Copyright (C) 2019 Marvell Technology Group Ltd.
++ */
++
++#include "armada-ap807.dtsi"
++
++/ {
++ model = "Marvell Armada AP807 Quad";
++ compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu0: cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a72", "arm,armv8";
++ reg = <0x000>;
++ enable-method = "psci";
++ #cooling-cells = <2>;
++ clocks = <&cpu_clk 0>;
++ };
++ cpu1: cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a72", "arm,armv8";
++ reg = <0x001>;
++ enable-method = "psci";
++ #cooling-cells = <2>;
++ clocks = <&cpu_clk 0>;
++ };
++ cpu2: cpu@100 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a72", "arm,armv8";
++ reg = <0x100>;
++ enable-method = "psci";
++ #cooling-cells = <2>;
++ clocks = <&cpu_clk 1>;
++ };
++ cpu3: cpu@101 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a72", "arm,armv8";
++ reg = <0x101>;
++ enable-method = "psci";
++ #cooling-cells = <2>;
++ clocks = <&cpu_clk 1>;
++ };
++ };
++};
+diff --git a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
+new file mode 100644
+index 000000000000..623010f3ca89
+--- /dev/null
++++ b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for Marvell Armada AP807
++ *
++ * Copyright (C) 2019 Marvell Technology Group Ltd.
++ */
++
++#define AP_NAME ap807
++#include "armada-ap80x.dtsi"
++
++/ {
++ model = "Marvell Armada AP807";
++ compatible = "marvell,armada-ap807";
++};
++
++&ap_syscon0 {
++ ap_clk: clock {
++ compatible = "marvell,ap807-clock";
++ #clock-cells = <1>;
++ };
++};
++
++&ap_syscon1 {
++ cpu_clk: clock-cpu {
++ compatible = "marvell,ap807-cpu-clock";
++ clocks = <&ap_clk 0>, <&ap_clk 1>;
++ #clock-cells = <1>;
++ };
++};
+--
+2.17.1
diff --git
a/target/linux/mvebu/patches-5.4/004-v5.5-arm64-dts-marvell-Add-AP807-quad-cache-description.patch
b/target/linux/mvebu/patches-5.4/004-v5.5-arm64-dts-marvell-Add-AP807-quad-cache-description.patch
new file mode 100644
index 0000000000..1a2fdb89b5
--- /dev/null
+++
b/target/linux/mvebu/patches-5.4/004-v5.5-arm64-dts-marvell-Add-AP807-quad-cache-description.patch
@@ -0,0 +1,91 @@
+From 30d53abdc60a6515f02f181e7c39b7b23d5fb3aa Mon Sep 17 00:00:00 2001
+From: Grzegorz Jaszczyk <j...@semihalf.com>
+Date: Fri, 4 Oct 2019 16:27:27 +0200
+Subject: [PATCH] arm64: dts: marvell: Add AP807-quad cache description
+
+Adding appropriate entries to device-tree allows the cache description
+to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.
+
+Signed-off-by: Grzegorz Jaszczyk <j...@semihalf.com>
+Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com>
+---
+ .../boot/dts/marvell/armada-ap807-quad.dtsi | 42 +++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+index 65364691257d..840466e143b4 100644
+--- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+@@ -22,6 +22,13 @@
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 0>;
++ i-cache-size = <0xc000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&l2_0>;
+ };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+@@ -30,6 +37,13 @@
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 0>;
++ i-cache-size = <0xc000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&l2_0>;
+ };
+ cpu2: cpu@100 {
+ device_type = "cpu";
+@@ -38,6 +52,13 @@
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 1>;
++ i-cache-size = <0xc000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&l2_1>;
+ };
+ cpu3: cpu@101 {
+ device_type = "cpu";
+@@ -46,6 +67,27 @@
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 1>;
++ i-cache-size = <0xc000>;
++ i-cache-line-size = <64>;
++ i-cache-sets = <256>;
++ d-cache-size = <0x8000>;
++ d-cache-line-size = <64>;
++ d-cache-sets = <256>;
++ next-level-cache = <&l2_1>;
++ };
++
++ l2_0: l2-cache0 {
++ compatible = "cache";
++ cache-size = <0x80000>;
++ cache-line-size = <64>;
++ cache-sets = <512>;
++ };
++
++ l2_1: l2-cache1 {
++ compatible = "cache";
++ cache-size = <0x80000>;
++ cache-line-size = <64>;
++ cache-sets = <512>;
+ };
+ };
+ };
+--
+2.17.1
diff --git
a/target/linux/mvebu/patches-5.4/005-v5.5-arm64-dts-marvell-Drop-PCIe-I-O-ranges-from-CP11x-fi.patch
b/target/linux/mvebu/patches-5.4/005-v5.5-arm64-dts-marvell-Drop-PCIe-I-O-ranges-from-CP11x-fi.patch
new file mode 100644
index 0000000000..88919f14eb
--- /dev/null
+++
b/target/linux/mvebu/patches-5.4/005-v5.5-arm64-dts-marvell-Drop-PCIe-I-O-ranges-from-CP11x-fi.patch
@@ -0,0 +1,145 @@
+From 1399672e48b573f6526b9ac78cfd50314f0b01a6 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.ray...@bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:30 +0200
+Subject: [PATCH] arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file
+
+As an example, Armada 70x0 and 80x0 SoC 0xf9000000 region points to
+RUNIT/SPICS0 while it is referenced in the DT as PCIe I/O memory
+range. This shows that I/O memory has never been used/working on the
+old SoCs despite the region being advertised. As PCIe I/O ranges will
+not be supported in newer SoCs using CP11x co-processors, let's
+simply drop them. It is not harmful in any case as PCIe device drivers
+can do it all with the regular mapped memory anyway.
+
+Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 2 --
+ .../boot/dts/marvell/armada-8040-mcbin.dtsi | 3 +--
+ arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 4 ----
+ arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 16 +++-------------
+ 4 files changed, 4 insertions(+), 21 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+index 4e78ccd207b7..ac28903ea409 100644
+--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+@@ -19,7 +19,6 @@
+ */
+ #define CP11X_NAME cp0
+ #define CP11X_BASE f2000000
+-#define CP11X_PCIE_IO_BASE 0xf9000000
+ #define CP11X_PCIE_MEM_BASE 0xf6000000
+ #define CP11X_PCIE0_BASE f2600000
+ #define CP11X_PCIE1_BASE f2620000
+@@ -29,7 +28,6 @@
+
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_IO_BASE
+ #undef CP11X_PCIE_MEM_BASE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+index d250f4b2bfed..572e2610e0a3 100644
+--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+@@ -179,8 +179,7 @@
+ num-lanes = <4>;
+ num-viewport = <8>;
+ reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
+- ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000
+- 0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
++ ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
+ phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
+ <&cp0_comphy2 0>, <&cp0_comphy3 0>;
+ phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
+diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+index ebb98836ec9c..902eed571bcc 100644
+--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+@@ -21,7 +21,6 @@
+ */
+ #define CP11X_NAME cp0
+ #define CP11X_BASE f2000000
+-#define CP11X_PCIE_IO_BASE 0xf9000000
+ #define CP11X_PCIE_MEM_BASE 0xf6000000
+ #define CP11X_PCIE0_BASE f2600000
+ #define CP11X_PCIE1_BASE f2620000
+@@ -31,7 +30,6 @@
+
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_IO_BASE
+ #undef CP11X_PCIE_MEM_BASE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+@@ -42,7 +40,6 @@
+ */
+ #define CP11X_NAME cp1
+ #define CP11X_BASE f4000000
+-#define CP11X_PCIE_IO_BASE 0xfd000000
+ #define CP11X_PCIE_MEM_BASE 0xfa000000
+ #define CP11X_PCIE0_BASE f4600000
+ #define CP11X_PCIE1_BASE f4620000
+@@ -52,7 +49,6 @@
+
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_IO_BASE
+ #undef CP11X_PCIE_MEM_BASE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+index 3e77cf34604c..7d1ab097453d 100644
+--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+@@ -10,7 +10,6 @@
+
+ #include "armada-common.dtsi"
+
+-#define CP11X_PCIEx_IO_BASE(iface) (CP11X_PCIE_IO_BASE + (iface *
0x10000))
+ #define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface *
0x1000000))
+ #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
+
+@@ -507,11 +506,8 @@
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+- ranges =
+- /* downstream I/O */
+- <0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0 CP11X_PCIEx_IO_BASE(0)
0 0x10000
+ /* non-prefetchable memory */
+- 0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0)
0 0xf00000>;
++ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0
CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22
IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+@@ -534,11 +530,8 @@
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+- ranges =
+- /* downstream I/O */
+- <0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0 CP11X_PCIEx_IO_BASE(1)
0 0x10000
+ /* non-prefetchable memory */
+- 0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1)
0 0xf00000>;
++ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0
CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24
IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+@@ -562,11 +555,8 @@
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+- ranges =
+- /* downstream I/O */
+- <0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0 CP11X_PCIEx_IO_BASE(2)
0 0x10000
+ /* non-prefetchable memory */
+- 0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2)
0 0xf00000>;
++ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0
CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23
IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+--
+2.17.1
diff --git
a/target/linux/mvebu/patches-5.4/006-v5.5-arm64-dts-marvell-Externalize-PCIe-macros-from-CP11x.patch
b/target/linux/mvebu/patches-5.4/006-v5.5-arm64-dts-marvell-Externalize-PCIe-macros-from-CP11x.patch
new file mode 100644
index 0000000000..7e649fe989
--- /dev/null
+++
b/target/linux/mvebu/patches-5.4/006-v5.5-arm64-dts-marvell-Externalize-PCIe-macros-from-CP11x.patch
@@ -0,0 +1,137 @@
+From 5f07b26e85dc86f017833ea745ff4e5b420280cd Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.ray...@bootlin.com>
+Date: Fri, 4 Oct 2019 16:27:31 +0200
+Subject: [PATCH] arm64: dts: marvell: Externalize PCIe macros from CP11x file
+
+PCIe macros are specific to CP110 and will not fit CP115
+constraints. To keep the same way the files are organized, just move
+some macros out of the CP11x generic file and define them directly in
+SoC DTSI, instead of defining single addresses in the SoC DTSI and
+reusing them in macros.
+
+In the end:
+* CP11X_PCIE_MEM_BASE SoC define is dropped
+* CP11X_PCIEx_MEM_BASE is moved out of the generic DT to be put in the
+ SoC files as it replaces the above definition.
+* As the CP11X_PCIEx_MEM_SIZE macro is also subject to change with
+ newer SoCs, we put it in the SoC files as well.
+
+Signed-off-by: Miquel Raynal <miquel.ray...@bootlin.com>
+Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com>
+---
+ arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++--
+ arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 12 ++++++++----
+ arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 9 ++++-----
+ 3 files changed, 16 insertions(+), 11 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+index ac28903ea409..293403a1a333 100644
+--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+@@ -19,7 +19,8 @@
+ */
+ #define CP11X_NAME cp0
+ #define CP11X_BASE f2000000
+-#define CP11X_PCIE_MEM_BASE 0xf6000000
++#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
++#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+ #define CP11X_PCIE0_BASE f2600000
+ #define CP11X_PCIE1_BASE f2620000
+ #define CP11X_PCIE2_BASE f2640000
+@@ -28,7 +29,8 @@
+
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIEx_MEM_BASE
++#undef CP11X_PCIEx_MEM_SIZE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+ #undef CP11X_PCIE2_BASE
+diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+index 902eed571bcc..ee67c70bf02e 100644
+--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+@@ -21,7 +21,8 @@
+ */
+ #define CP11X_NAME cp0
+ #define CP11X_BASE f2000000
+-#define CP11X_PCIE_MEM_BASE 0xf6000000
++#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
++#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+ #define CP11X_PCIE0_BASE f2600000
+ #define CP11X_PCIE1_BASE f2620000
+ #define CP11X_PCIE2_BASE f2640000
+@@ -30,7 +31,8 @@
+
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIEx_MEM_BASE
++#undef CP11X_PCIEx_MEM_SIZE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+ #undef CP11X_PCIE2_BASE
+@@ -40,7 +42,8 @@
+ */
+ #define CP11X_NAME cp1
+ #define CP11X_BASE f4000000
+-#define CP11X_PCIE_MEM_BASE 0xfa000000
++#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
++#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+ #define CP11X_PCIE0_BASE f4600000
+ #define CP11X_PCIE1_BASE f4620000
+ #define CP11X_PCIE2_BASE f4640000
+@@ -49,7 +52,8 @@
+
+ #undef CP11X_NAME
+ #undef CP11X_BASE
+-#undef CP11X_PCIE_MEM_BASE
++#undef CP11X_PCIEx_MEM_BASE
++#undef CP11X_PCIEx_MEM_SIZE
+ #undef CP11X_PCIE0_BASE
+ #undef CP11X_PCIE1_BASE
+ #undef CP11X_PCIE2_BASE
+diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+index 7d1ab097453d..9dcf16beabf5 100644
+--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
++++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+@@ -10,8 +10,7 @@
+
+ #include "armada-common.dtsi"
+
+-#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface *
0x1000000))
+-#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
++#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) +
CP11X_PCIEx_MEM_SIZE(iface))
+
+ / {
+ /*
+@@ -507,7 +506,7 @@
+
+ bus-range = <0 0xff>;
+ /* non-prefetchable memory */
+- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0
CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
++ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0
CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22
IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+@@ -531,7 +530,7 @@
+
+ bus-range = <0 0xff>;
+ /* non-prefetchable memory */
+- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0
CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
++ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0
CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24
IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+@@ -556,7 +555,7 @@
+
+ bus-range = <0 0xff>;
+ /* non-prefetchable memory */
+- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0
CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
++ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0
CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23
IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+--
+2.17.1
--
2.17.1
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