On Thu, May 6, 2021 at 7:32 PM Denis Kalashnikov <denis281...@gmail.com> wrote:
> + /*
> + * MFD: NAND plus GPIO-controller. They use/share SoC GPIO lines.
> Some of the
> + * GPIO lines are multiplexed by a 8-bit latch (LVC573).
> + * NAND is controlled by GPIO lines (bitbang), also some NAND control
> lines
> + * (nCE, ALE, CLE, READ) and data lines are multiplexed by a latch.
> So driver
> + * set control lines, enable latch ("latched them") and then transfer
> data.
> + * Several lines of the latch (not used for NAND control lines) are
> used
> + * as general-purpose GPIO. NAND ECC format is Mikrotik specific.
> + */
> + /*
> +
> +-----------+
> +
> | |
> ++-----------------+
> | |
> +| |
> | |
> +| |
> | |
> +| |
> | | 3-4 lines
> +| |
> | +--------
> +| G | 8 lines
> | 8-bit | GPIO
> +| P
> +-------+-------------------------------------------------+ |
> (leds, SSR nCS)
> +| I | |
> | Latch |
> +| O | |
> | |
> +| s | |
> | LVC573 | 4 lines
> +| | |
> | +-------+
> +| | |
> | | |
> +| | |
> | | |
> +| | |
> | | |
> +| | |
> | | |
> +| | |
> | | |
> +| | | 8
> +-----------+ |
> +| | |
> |
> +| | | l
> |
> +| | | i
> |
> +| SoC | | n
> |
> +| | | e
> |
> +| | | s
> +----------------------------------+ |
> +| | | |
> | |
> +| | | |
> C | |
> +| | | |
> | nCE, CLE, ALE, |
> +| | | |
> O +----------------+
> +| | | | D
> | READ
> +| | | |
> N |
> +| | | | A
> |
> +| | | | N A N D
> T |
> +| | +-----------------+ T
> |
> +| | |
> R | nRW, RDY
> +| | | A
> +----------+
> +| | |
> O | |
> +| | |
> | |
> +| | |
> L | |
> +| | |
> | |
> +| G | |
> | |
> +| P |
> +----------------------------------+ |
> +| I | 2 lines
> |
> +| O
> +-----------------------------------------------------------------------+
> +| s |
> +| |
> ++-----------------+
This drawing has a small drawback. Looks like NAND RDY has no
dedicated line and shares GPIO with the NAND Data#4.
> + nand_gpio {
> + compatible = "mikrotik,nand-gpio-latch";
> +
> + /* NAND control gpios */
> + nand-read-gpios = <&gpio 3 0>; /* Read */
> + nand-rdy-gpios = <&gpio 4 0>; /* Ready */
> + nand-nrw-gpios = <&gpio 12 GPIO_ACTIVE_LOW>; /* Read/Write
> Strobe */
> + nand-nce-gpios = <&gpio 13 GPIO_ACTIVE_LOW>; /* Chip Enable
> */
> + nand-cle-gpios = <&gpio 14 0>; /* Command Latch */
> + nand-ale-gpios = <&gpio 15 0>; /* Address Latch */
> +
> + /* Latch Enable */
> + nle-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
> +
> + nand-data-gpios = <&gpio 0 0>,
> + <&gpio 1 0>,
> + <&gpio 2 0>,
> + <&gpio 3 0>,
> + <&gpio 4 0>,
> + <&gpio 13 0>,
> + <&gpio 14 0>,
> + <&gpio 15 0>;
> +
> + latch-gpios = <&gpio 0 GPIO_ACTIVE_LOW>,
> + <&gpio 1 GPIO_ACTIVE_LOW>,
> + <&gpio 2 GPIO_ACTIVE_LOW>;
This driver is highly board specific and we use DTS not to configure
it, but mostly to document HW interconnections. Also it is unusual
when a same GPIO line is referenced multiple times from different
properties. So maybe we should use a single property with magic
positions and accomplish interconnection description with comments?
E.g.
gpios = <&gpio 0 ...>, /* NAND Data#0 / SSR strobe (SPI CS) */
<&gpio 1 ...>, /* NAND Data#1 / Power LED */
<&gpio 2 ...>, /* NAND Data#2 / User LED */
<&gpio 3 ...>, /* NAND Data#3 / NAND Read */
<&gpio 4 ...>, /* NAND Data#4 / NAND RDY */
<&gpio 13 ...>, /* NAND Data#5 / NAND nCE */
<&gpio 14 ...>, /* NAND Data#6 / NAND CLE */
<&gpio 15 ...>, /* NAND Data#7 / NAND ALE */
<&gpio 11 ...>; /* Latch enable */
This will simplify the driver code.
--
Sergey
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