This patch adds many registers and values for QCA956x GMAC interface. QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG, QCA956X_PLL_ETH_XMII_CONTROL_REG and QCA956X_ETH_CFG_RGMII_EN names are fixed to match original names.
Values are taken from U-Boot 1.1.4 of CAF. Signed-off-by: Julien Dusser <julien.dus...@free.fr> Signed-off-by: Sander Vanheule <san...@svanheule.net> --- .../920-qca956x-add-more-registers.patch | 186 ++++++++++++++++++ .../920-qca956x-add-more-registers.patch | 186 ++++++++++++++++++ 2 files changed, 372 insertions(+) create mode 100644 target/linux/ath79/patches-4.19/920-qca956x-add-more-registers.patch create mode 100644 target/linux/ath79/patches-5.4/920-qca956x-add-more-registers.patch diff --git a/target/linux/ath79/patches-4.19/920-qca956x-add-more-registers.patch b/target/linux/ath79/patches-4.19/920-qca956x-add-more-registers.patch new file mode 100644 index 0000000000..961bfe05ba --- /dev/null +++ b/target/linux/ath79/patches-4.19/920-qca956x-add-more-registers.patch @@ -0,0 +1,186 @@ +MIPS: ath79: add lots of missing registers for QCA956x SoCs + +This patch adds many registers and values for QCA956x GMAC interface. + +QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG, QCA956X_PLL_ETH_XMII_CONTROL_REG +and QCA956X_ETH_CFG_RGMII_EN names are fixed to match original names. + +Values are taken from U-Boot 1.1.4 of CAF. + +Signed-off-by: Julien Dusser <julien.dus...@free.fr> +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -438,8 +438,18 @@ + #define QCA956X_PLL_DDR_CONFIG_REG 0x08 + #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c + #define QCA956X_PLL_CLK_CTRL_REG 0x10 +-#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28 +-#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30 ++#define QCA956X_PLL_PCIE_PLL_CONFIG_REG 0x14 ++#define QCA956X_PLL_PCIE_PLL_DITHER_DIV_MAX_REG 0x18 ++#define QCA956X_PLL_PCIE_PLL_DITHER_DIV_MIN_REG 0x1c ++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_REG 0x28 ++#define QCA956X_PLL_CURRENT_PCIE_PLL_DITHER_REG 0x2c ++#define QCA956X_PLL_ETH_XMII_REG 0x30 ++#define QCA956X_PLL_BB_PLL_CONFIG_REG 0x34 ++#define QCA956X_PLL_DDR_PLL_DITHER1_REG 0x38 ++#define QCA956X_PLL_DDR_PLL_DITHER2_REG 0x3c ++#define QCA956X_PLL_CPU_PLL_DITHER1_REG 0x40 ++#define QCA956X_PLL_CPU_PLL_DITHER2_REG 0x44 ++#define QCA956X_PLL_ETH_SGMII_REG 0x48 + #define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c + + #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +@@ -1333,24 +1343,39 @@ + * QCA956X GMAC Interface + */ + +-#define QCA956X_GMAC_REG_ETH_CFG 0x00 +-#define QCA956X_GMAC_REG_SGMII_RESET 0x14 +-#define QCA956X_GMAC_REG_SGMII_SERDES 0x18 +-#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c +-#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34 +-#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58 +- +-#define QCA956X_ETH_CFG_RGMII_EN BIT(0) ++#define QCA956X_GMAC_REG_ETH_CFG 0x00 ++#define QCA956X_GMAC_REG_SGMII_RESET 0x14 ++#define QCA956X_GMAC_REG_SGMII_SERDES 0x18 ++#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c ++#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34 ++#define QCA956X_GMAC_REG_SGMII_MAC_RX_CONFIG 0x38 ++#define QCA956X_GMAC_REG_ETH_SGMII 0x48 ++#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58 ++#define QCA956X_GMAC_REG_SGMII_INTERRUPT 0x5c ++#define QCA956X_GMAC_REG_SGMII_INTERRUPT_MASK 0x60 ++ ++#define QCA956X_ETH_CFG_RGMII_GE0 BIT(0) ++#define QCA956X_ETH_CFG_MII_GE0 BIT(1) ++#define QCA956X_ETH_CFG_GMII_GE0 BIT(2) ++#define QCA956X_ETH_CFG_MII_GE0_MASTER BIT(3) ++#define QCA956X_ETH_CFG_MII_GE0_SLAVE BIT(4) ++#define QCA956X_ETH_CFG_GE0_ERR BIT(5) + #define QCA956X_ETH_CFG_GE0_SGMII BIT(6) + #define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7) + #define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8) + #define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9) + #define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10) ++#define QCA956X_ETH_CFG_MII_CNTL_SPEED BIT(11) ++#define QCA956X_ETH_CFG_RMII_GE0_MASTER BIT(12) + #define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + #define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3 + #define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14 + #define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3 + #define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16 ++#define QCA956X_ETH_CFG_TXD_DELAY_MASK 0x3 ++#define QCA956X_ETH_CFG_TXD_DELAY_SHIFT 18 ++#define QCA956X_ETH_CFG_TXE_DELAY_MASK 0x3 ++#define QCA956X_ETH_CFG_TXE_DELAY_SHIFT 20 + + #define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0 + #define QCA956X_SGMII_RESET_RX_CLK_N BIT(0) +@@ -1359,25 +1384,87 @@ + #define QCA956X_SGMII_RESET_TX_125M_N BIT(3) + #define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4) + +-#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3 +-#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1 +-#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7 +-#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4 +-#define QCA956X_SGMII_SERDES_PLL_BW BIT(8) +-#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9) +-#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10) +-#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) +-#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16) +-#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17) +-#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 +-#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf +-#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27 +-#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf +- ++#define QCA956X_SGMII_SERDES_RX_IMPEDANCE BIT(0) ++#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3 ++#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1 ++#define QCA956X_SGMII_SERDES_HALF_TX BIT(3) ++#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7 ++#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4 ++#define QCA956X_SGMII_SERDES_TX_IMPEDANCE BIT(7) ++#define QCA956X_SGMII_SERDES_PLL_BW BIT(8) ++#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9) ++#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10) ++#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) ++#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16) ++#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17) ++#define QCA956X_SGMII_SERDES_THRESHOLD_CTRL_SHIFT 18 ++#define QCA956X_SGMII_SERDES_THRESHOLD_CTRL_MASK 0x3 ++#define QCA956X_SGMII_SERDES_FIBER_MODE_SHIFT 20 ++#define QCA956X_SGMII_SERDES_FIBER_MODE_MASK 0x3 ++#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 ++#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf ++#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27 ++#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf ++ ++#define QCA956X_MR_AN_CONTROL_SPEED_SEL1 BIT(6) ++#define QCA956X_MR_AN_CONTROL_DUPLEX_MODE BIT(8) ++#define QCA956X_MR_AN_CONTROL_RESTART_AN BIT(9) ++#define QCA956X_MR_AN_CONTROL_POWER_DOWN BIT(11) + #define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12) ++#define QCA956X_MR_AN_CONTROL_SPEED_SEL0 BIT(13) ++#define QCA956X_MR_AN_CONTROL_LOOPBACK BIT(14) + #define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15) + +-#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 +-#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 ++#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 ++#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 ++#define QCA956X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE BIT(3) ++#define QCA956X_SGMII_CONFIG_MR_REG4_CHANGED BIT(4) ++#define QCA956X_SGMII_CONFIG_FORCE_SPEED BIT(5) ++#define QCA956X_SGMII_CONFIG_SPEED_SHIFT 6 ++#define QCA956X_SGMII_CONFIG_SPEED_MASK 0x3 ++#define QCA956X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK BIT(8) ++#define QCA956X_SGMII_CONFIG_NEXT_PAGE_LOADED BIT(9) ++#define QCA956X_SGMII_CONFIG_MDIO_ENABLE BIT(10) ++#define QCA956X_SGMII_CONFIG_MDIO_PULSE BIT(11) ++#define QCA956X_SGMII_CONFIG_MDIO_COMPLETE BIT(12) ++#define QCA956X_SGMII_CONFIG_PRBS_ENABLE BIT(13) ++#define QCA956X_SGMII_CONFIG_BERT_ENABLE BIT(14) ++ ++#define QCA956X_SGMII_MAC_RX_CONFIG_RES0 BIT(0) ++#define QCA956X_SGMII_MAC_RX_CONFIG_PAUSE BIT(7) ++#define QCA956X_SGMII_MAC_RX_CONFIG_ASM_PAUSE BIT(8) ++#define QCA956X_SGMII_MAC_RX_CONFIG_SPEED_MODE_SHIFT 10 ++#define QCA956X_SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK 0x3 ++#define QCA956X_SGMII_MAC_RX_CONFIG_DUPLEX_MODE BIT(12) ++#define QCA956X_SGMII_MAC_RX_CONFIG_ACK BIT(14) ++#define QCA956X_SGMII_MAC_RX_CONFIG_LINK BIT(15) ++ ++#define QCA956X_ETH_SGMII_PHASE0_COUNT_SHIFT 0 ++#define QCA956X_ETH_SGMII_PHASE0_COUNT_MASK 0xff ++#define QCA956X_ETH_SGMII_PHASE1_COUNT_SHIFT 8 ++#define QCA956X_ETH_SGMII_PHASE1_COUNT_MASK 0xff ++#define QCA956X_ETH_SGMII_GIGE BIT(24) ++#define QCA956X_ETH_SGMII_CLK_SEL BIT(25) ++#define QCA956X_ETH_SGMII_TX_DELAY_SHIFT 26 ++#define QCA956X_ETH_SGMII_TX_DELAY_MASK 0x3 ++#define QCA956X_ETH_SGMII_RX_DELAY_SHIFT 28 ++#define QCA956X_ETH_SGMII_RX_DELAY_MASK 0x3 ++#define QCA956X_ETH_SGMII_GIGE_QUAD BIT(30) ++#define QCA956X_ETH_SGMII_TX_INVERT BIT(31) ++ ++#define QCA956X_SGMII_DEBUG_TX_STATE_SHIFT 0 ++#define QCA956X_SGMII_DEBUG_TX_STATE_MASK 0xff ++#define QCA956X_SGMII_DEBUG_RX_STATE_SHIFT 8 ++#define QCA956X_SGMII_DEBUG_RX_STATE_MSB 0xff ++#define QCA956X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16 ++#define QCA956X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff ++#define QCA956X_SGMII_DEBUG_ARB_STATE_SHIFT 24 ++#define QCA956X_SGMII_DEBUG_ARB_STATE_MASK 0xf ++ ++#define QCA956X_SGMII_INTERRUPT_INTR_SHIFT 0 ++#define QCA956X_SGMII_INTERRUPT_INTR_MASK 0xff ++ ++#define QCA956X_SGMII_INTERRUPT_MASK_MASK_SHIFT 0 ++#define QCA956X_SGMII_INTERRUPT_MASK_MASK_MASK 0xff + + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ath79/patches-5.4/920-qca956x-add-more-registers.patch b/target/linux/ath79/patches-5.4/920-qca956x-add-more-registers.patch new file mode 100644 index 0000000000..946669666f --- /dev/null +++ b/target/linux/ath79/patches-5.4/920-qca956x-add-more-registers.patch @@ -0,0 +1,186 @@ +MIPS: ath79: add lots of missing registers for QCA956x SoCs + +This patch adds many registers and values for QCA956x GMAC interface. + +QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG, QCA956X_PLL_ETH_XMII_CONTROL_REG +and QCA956X_ETH_CFG_RGMII_EN names are fixed to match original names. + +Values are taken from U-Boot 1.1.4 of CAF. + +Signed-off-by: Julien Dusser <julien.dus...@free.fr> +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -435,8 +435,18 @@ + #define QCA956X_PLL_DDR_CONFIG_REG 0x08 + #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c + #define QCA956X_PLL_CLK_CTRL_REG 0x10 +-#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28 +-#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30 ++#define QCA956X_PLL_PCIE_PLL_CONFIG_REG 0x14 ++#define QCA956X_PLL_PCIE_PLL_DITHER_DIV_MAX_REG 0x18 ++#define QCA956X_PLL_PCIE_PLL_DITHER_DIV_MIN_REG 0x1c ++#define QCA956X_PLL_SWITCH_CLOCK_SPARE_REG 0x28 ++#define QCA956X_PLL_CURRENT_PCIE_PLL_DITHER_REG 0x2c ++#define QCA956X_PLL_ETH_XMII_REG 0x30 ++#define QCA956X_PLL_BB_PLL_CONFIG_REG 0x34 ++#define QCA956X_PLL_DDR_PLL_DITHER1_REG 0x38 ++#define QCA956X_PLL_DDR_PLL_DITHER2_REG 0x3c ++#define QCA956X_PLL_CPU_PLL_DITHER1_REG 0x40 ++#define QCA956X_PLL_CPU_PLL_DITHER2_REG 0x44 ++#define QCA956X_PLL_ETH_SGMII_REG 0x48 + #define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c + + #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +@@ -1330,24 +1340,39 @@ + * QCA956X GMAC Interface + */ + +-#define QCA956X_GMAC_REG_ETH_CFG 0x00 +-#define QCA956X_GMAC_REG_SGMII_RESET 0x14 +-#define QCA956X_GMAC_REG_SGMII_SERDES 0x18 +-#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c +-#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34 +-#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58 +- +-#define QCA956X_ETH_CFG_RGMII_EN BIT(0) ++#define QCA956X_GMAC_REG_ETH_CFG 0x00 ++#define QCA956X_GMAC_REG_SGMII_RESET 0x14 ++#define QCA956X_GMAC_REG_SGMII_SERDES 0x18 ++#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c ++#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34 ++#define QCA956X_GMAC_REG_SGMII_MAC_RX_CONFIG 0x38 ++#define QCA956X_GMAC_REG_ETH_SGMII 0x48 ++#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58 ++#define QCA956X_GMAC_REG_SGMII_INTERRUPT 0x5c ++#define QCA956X_GMAC_REG_SGMII_INTERRUPT_MASK 0x60 ++ ++#define QCA956X_ETH_CFG_RGMII_GE0 BIT(0) ++#define QCA956X_ETH_CFG_MII_GE0 BIT(1) ++#define QCA956X_ETH_CFG_GMII_GE0 BIT(2) ++#define QCA956X_ETH_CFG_MII_GE0_MASTER BIT(3) ++#define QCA956X_ETH_CFG_MII_GE0_SLAVE BIT(4) ++#define QCA956X_ETH_CFG_GE0_ERR BIT(5) + #define QCA956X_ETH_CFG_GE0_SGMII BIT(6) + #define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7) + #define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8) + #define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9) + #define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10) ++#define QCA956X_ETH_CFG_MII_CNTL_SPEED BIT(11) ++#define QCA956X_ETH_CFG_RMII_GE0_MASTER BIT(12) + #define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + #define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3 + #define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14 + #define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3 + #define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16 ++#define QCA956X_ETH_CFG_TXD_DELAY_MASK 0x3 ++#define QCA956X_ETH_CFG_TXD_DELAY_SHIFT 18 ++#define QCA956X_ETH_CFG_TXE_DELAY_MASK 0x3 ++#define QCA956X_ETH_CFG_TXE_DELAY_SHIFT 20 + + #define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0 + #define QCA956X_SGMII_RESET_RX_CLK_N BIT(0) +@@ -1356,25 +1381,87 @@ + #define QCA956X_SGMII_RESET_TX_125M_N BIT(3) + #define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4) + +-#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3 +-#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1 +-#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7 +-#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4 +-#define QCA956X_SGMII_SERDES_PLL_BW BIT(8) +-#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9) +-#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10) +-#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) +-#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16) +-#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17) +-#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 +-#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf +-#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27 +-#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf +- ++#define QCA956X_SGMII_SERDES_RX_IMPEDANCE BIT(0) ++#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3 ++#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1 ++#define QCA956X_SGMII_SERDES_HALF_TX BIT(3) ++#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7 ++#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4 ++#define QCA956X_SGMII_SERDES_TX_IMPEDANCE BIT(7) ++#define QCA956X_SGMII_SERDES_PLL_BW BIT(8) ++#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9) ++#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10) ++#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) ++#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16) ++#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17) ++#define QCA956X_SGMII_SERDES_THRESHOLD_CTRL_SHIFT 18 ++#define QCA956X_SGMII_SERDES_THRESHOLD_CTRL_MASK 0x3 ++#define QCA956X_SGMII_SERDES_FIBER_MODE_SHIFT 20 ++#define QCA956X_SGMII_SERDES_FIBER_MODE_MASK 0x3 ++#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 ++#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf ++#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27 ++#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf ++ ++#define QCA956X_MR_AN_CONTROL_SPEED_SEL1 BIT(6) ++#define QCA956X_MR_AN_CONTROL_DUPLEX_MODE BIT(8) ++#define QCA956X_MR_AN_CONTROL_RESTART_AN BIT(9) ++#define QCA956X_MR_AN_CONTROL_POWER_DOWN BIT(11) + #define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12) ++#define QCA956X_MR_AN_CONTROL_SPEED_SEL0 BIT(13) ++#define QCA956X_MR_AN_CONTROL_LOOPBACK BIT(14) + #define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15) + +-#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 +-#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 ++#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 ++#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 ++#define QCA956X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE BIT(3) ++#define QCA956X_SGMII_CONFIG_MR_REG4_CHANGED BIT(4) ++#define QCA956X_SGMII_CONFIG_FORCE_SPEED BIT(5) ++#define QCA956X_SGMII_CONFIG_SPEED_SHIFT 6 ++#define QCA956X_SGMII_CONFIG_SPEED_MASK 0x3 ++#define QCA956X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK BIT(8) ++#define QCA956X_SGMII_CONFIG_NEXT_PAGE_LOADED BIT(9) ++#define QCA956X_SGMII_CONFIG_MDIO_ENABLE BIT(10) ++#define QCA956X_SGMII_CONFIG_MDIO_PULSE BIT(11) ++#define QCA956X_SGMII_CONFIG_MDIO_COMPLETE BIT(12) ++#define QCA956X_SGMII_CONFIG_PRBS_ENABLE BIT(13) ++#define QCA956X_SGMII_CONFIG_BERT_ENABLE BIT(14) ++ ++#define QCA956X_SGMII_MAC_RX_CONFIG_RES0 BIT(0) ++#define QCA956X_SGMII_MAC_RX_CONFIG_PAUSE BIT(7) ++#define QCA956X_SGMII_MAC_RX_CONFIG_ASM_PAUSE BIT(8) ++#define QCA956X_SGMII_MAC_RX_CONFIG_SPEED_MODE_SHIFT 10 ++#define QCA956X_SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK 0x3 ++#define QCA956X_SGMII_MAC_RX_CONFIG_DUPLEX_MODE BIT(12) ++#define QCA956X_SGMII_MAC_RX_CONFIG_ACK BIT(14) ++#define QCA956X_SGMII_MAC_RX_CONFIG_LINK BIT(15) ++ ++#define QCA956X_ETH_SGMII_PHASE0_COUNT_SHIFT 0 ++#define QCA956X_ETH_SGMII_PHASE0_COUNT_MASK 0xff ++#define QCA956X_ETH_SGMII_PHASE1_COUNT_SHIFT 8 ++#define QCA956X_ETH_SGMII_PHASE1_COUNT_MASK 0xff ++#define QCA956X_ETH_SGMII_GIGE BIT(24) ++#define QCA956X_ETH_SGMII_CLK_SEL BIT(25) ++#define QCA956X_ETH_SGMII_TX_DELAY_SHIFT 26 ++#define QCA956X_ETH_SGMII_TX_DELAY_MASK 0x3 ++#define QCA956X_ETH_SGMII_RX_DELAY_SHIFT 28 ++#define QCA956X_ETH_SGMII_RX_DELAY_MASK 0x3 ++#define QCA956X_ETH_SGMII_GIGE_QUAD BIT(30) ++#define QCA956X_ETH_SGMII_TX_INVERT BIT(31) ++ ++#define QCA956X_SGMII_DEBUG_TX_STATE_SHIFT 0 ++#define QCA956X_SGMII_DEBUG_TX_STATE_MASK 0xff ++#define QCA956X_SGMII_DEBUG_RX_STATE_SHIFT 8 ++#define QCA956X_SGMII_DEBUG_RX_STATE_MSB 0xff ++#define QCA956X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16 ++#define QCA956X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff ++#define QCA956X_SGMII_DEBUG_ARB_STATE_SHIFT 24 ++#define QCA956X_SGMII_DEBUG_ARB_STATE_MASK 0xf ++ ++#define QCA956X_SGMII_INTERRUPT_INTR_SHIFT 0 ++#define QCA956X_SGMII_INTERRUPT_INTR_MASK 0xff ++ ++#define QCA956X_SGMII_INTERRUPT_MASK_MASK_SHIFT 0 ++#define QCA956X_SGMII_INTERRUPT_MASK_MASK_MASK 0xff + + #endif /* __ASM_MACH_AR71XX_REGS_H */ -- 2.26.2 _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
