Hello Adrian, On 9/23/19 3:34 PM, Adrian Schmutzler wrote: > qxwlan,e2600ac-c1 |\ > qxwlan,e2600ac-c2) > - ucidef_set_interfaces_lan_wan "eth0" "eth1" > ucidef_add_switch "switch0" \ > "0u@eth0" "3:lan" "4:lan" "0u@eth1" "5:wan" > ;;
While from the coding it looks like multiple cpu port distribution is supported, I'm not sure if this is handled correctly for untagged ports. Furthermore, the switch initialization is a bit "messed up", as the mapping between external phy <-> ess-switch <--> cpu interfaces is not very obvious. 1) All devices with eth1 interface have it utilize the 5th PHY (displayed as switchport 5) 2) All devices with a QCA8072 utilize PHY 4 (displayed as switchport 4) for eth0 3) Devices using an RGMII attached PHY (currently only MR33) do not have a switch-construct. So if we really want to clean this up correctly, there are some more things to consider (which also brings the opportunity to simplify this further). Also, the first point gives you the opportunity to test the dual-untagged-cpuport on another ipq40xx device. :) On the other hand there's ipqess and qca8k on the horizon to end the ar40xx mess. But i don't think this is a showstopper for this. Best wishes David _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
