04/09/2019 12:07, Enrico Mioso:
Hi there!So I am trying to get ethernet working on this AR10 device. It has 3 GPHYs: gphy0: gphy@20 { compatible = "lantiq,xrx300-gphy"; reg = <0x20 0x4>; resets = <&reset0 31 30>, <&reset1 7 7>; reset-names = "gphy", "gphy2"; }; gphy1: gphy@58 { compatible = "lantiq,xrx300-gphy"; reg = <0x58 0x4>; resets = <&reset0 29 28>, <&reset1 6 6>; reset-names = "gphy", "gphy2"; }; gphy2: gphy@ac { compatible = "lantiq,xrx300-gphy"; reg = <0xac 0x4>; resets = <&reset0 27 26>, <&reset1 5 5>; reset-names = "gphy", "gphy2"; }; And firmware load addresses for GPHYs are correct as per the vendor code:#define IFX_RCU_GPHY0_FW_ADDR ((volatile u32*)(IFX_RCU + 0x0020)) #define IFX_RCU_GPHY1_FW_ADDR ((volatile u32*)(IFX_RCU + 0x0058)) #define IFX_RCU_GPHY2_FW_ADDR ((volatile u32*)(IFX_RCU + 0x00AC))But driver was failing to initialize due to missing clock gates. In sysctrl.c, we have: clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY); // OK for GPHY0 clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY); //problem for GPHY1
The first parameter of clkdev_add_pmu doesn't match your dts. It has to be "1f203058.gphy"
Regards Mathias _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
