On Monday, March 25, 2019 2:16:04 PM CET Petr Štetiar wrote: > Thanks! Merged into my staging tree at > https://git.openwrt.org/openwrt/staging/ynezz.git
https://patchwork.ozlabs.org/patch/1034614/#2088615 So, I think in order for this to "work as expected" the sysclock in the mt7621.dtsi should be at 220 MHz (as in the upstream drivers/staging/mt7621-dts/mt7621.dtsi) instead of 50 MHz. That said, I don't think this will break anything since the mt7621-spi driver from 0043-spi-add-mt7621-support.patch, just limits it at the fake "25 Mhz" (which should be ~110 MHz). So, this will just look odd and makes no sense at the first glance. Cheers, Christian _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
