On 31/12/15 12:22, Roman Yeryomin wrote: > On 29 December 2015 at 12:14, Kevin Darbyshire-Bryant > <ke...@darbyshire-bryant.me.uk> wrote: > > Kevin, are you sure this works? > I don't have /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size > on my Archer C7 Hi Roman,
Perf ran and didn't barf when I tried...however I'm new to perf so maybe I didn't look in the right place. I also wonder if that sys file entry is only enabled when kernel perf config is enabled too. > I did a little bit more simple way adding a header from eglibc. If > anybody interested I can submit the patch for RFC. Personally, I'd say anything that helps performance investigations on 'under powered' SoC devices is a good thing, helpful & useful. Kevin > > > Regards, > Roman
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