Tested on Toradex Apalis iMX6 Quad 2GB IT V1.1A module on Ixora board
with Mikrotik R11e-2HnD and Quectel EC20 Mini PCIe modules.
Signed-off-by: Petr Štetiar <yn...@true.cz>
---
target/linux/imx6/image/Makefile | 2 +
...6-Add-support-for-Toradex-Apalis-modules-.patch | 1996 ++++++++++++++++++++
...dd-reset-function-for-reseting-downstream.patch | 79 +
target/linux/imx6/profiles/130-toradex.mk | 27 +
4 files changed, 2104 insertions(+)
create mode 100644
target/linux/imx6/patches-4.1/200-ARM-dts-imx6-Add-support-for-Toradex-Apalis-modules-.patch
create mode 100644
target/linux/imx6/patches-4.1/300-pcie-imx6-add-reset-function-for-reseting-downstream.patch
create mode 100644 target/linux/imx6/profiles/130-toradex.mk
diff --git a/target/linux/imx6/image/Makefile b/target/linux/imx6/image/Makefile
index d5bab30..0dadf0b 100644
--- a/target/linux/imx6/image/Makefile
+++ b/target/linux/imx6/image/Makefile
@@ -110,6 +110,8 @@ Image/BuildKernel/Template/VENTANA=$(foreach dts,$(shell
echo $(VENTANA_DTS)),$(
Image/InstallKernel/Template/VENTANA=$(call
Image/InstallKernel/Template,$(VENTANA_DTS))
Image/ubifs/VENTANA=$(call ubifs_imx_gateworks_ventana)
+Image/BuildKernel/Template/APALIS=$(foreach dts,$(shell echo
$(APALIS_DTS)),$(call Image/BuildKernel/Template,$(dts)))
+Image/InstallKernel/Template/APALIS=$(call
Image/InstallKernel/Template,$(APALIS_DTS))
define Image/BuildKernel
$(call Image/BuildKernel/Template/$(PROFILE))
diff --git
a/target/linux/imx6/patches-4.1/200-ARM-dts-imx6-Add-support-for-Toradex-Apalis-modules-.patch
b/target/linux/imx6/patches-4.1/200-ARM-dts-imx6-Add-support-for-Toradex-Apalis-modules-.patch
new file mode 100644
index 0000000..74c2718
--- /dev/null
+++
b/target/linux/imx6/patches-4.1/200-ARM-dts-imx6-Add-support-for-Toradex-Apalis-modules-.patch
@@ -0,0 +1,1996 @@
+From a9b5bec66c768274493a4d583b7adba366c80470 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <yn...@true.cz>
+Date: Wed, 14 Oct 2015 16:37:43 +0200
+Subject: [PATCH 1/3] ARM: dts: imx6: Add support for Toradex Apalis modules
+ and boards
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+* includes support for Eval and Ixora boards
+* hand picked from toradex_imx_3.14.28_1.0.0_ga-next branch
+
+Signed-off-by: Petr Štetiar <yn...@true.cz>
+---
+ arch/arm/boot/dts/Makefile | 4 +
+ arch/arm/boot/dts/imx6q-apalis-eval.dts | 25 +
+ arch/arm/boot/dts/imx6q-apalis-ixora.dts | 25 +
+ arch/arm/boot/dts/imx6q-apalis_v1_0-eval.dts | 29 +
+ arch/arm/boot/dts/imx6q-apalis_v1_0-ixora.dts | 29 +
+ arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi | 357 ++++++++
+ arch/arm/boot/dts/imx6qdl-apalis-ixora.dtsi | 333 ++++++++
+ arch/arm/boot/dts/imx6qdl-apalis.dtsi | 1107 +++++++++++++++++++++++++
+ 8 files changed, 1909 insertions(+)
+ create mode 100644 arch/arm/boot/dts/imx6q-apalis-eval.dts
+ create mode 100644 arch/arm/boot/dts/imx6q-apalis-ixora.dts
+ create mode 100644 arch/arm/boot/dts/imx6q-apalis_v1_0-eval.dts
+ create mode 100644 arch/arm/boot/dts/imx6q-apalis_v1_0-ixora.dts
+ create mode 100644 arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi
+ create mode 100644 arch/arm/boot/dts/imx6qdl-apalis-ixora.dtsi
+ create mode 100644 arch/arm/boot/dts/imx6qdl-apalis.dtsi
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 992736b..2a5aff2 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -277,6 +277,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
+ imx6dl-udoo.dtb \
+ imx6dl-wandboard.dtb \
+ imx6dl-wandboard-revb1.dtb \
++ imx6q-apalis-eval.dtb \
++ imx6q-apalis_v1_0-eval.dtb \
++ imx6q-apalis-ixora.dtb \
++ imx6q-apalis_v1_0-ixora.dtb \
+ imx6q-arm2.dtb \
+ imx6q-cm-fx6.dtb \
+ imx6q-cubox-i.dtb \
+diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts
b/arch/arm/boot/dts/imx6q-apalis-eval.dts
+new file mode 100644
+index 0000000..1f49c7a
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
+@@ -0,0 +1,25 @@
++/*
++ * Copyright 2014-2015 Toradex AG
++ * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++#include "imx6q.dtsi"
++#include "imx6qdl-apalis.dtsi"
++#include "imx6qdl-apalis-eval.dtsi"
++
++/ {
++ model = "Toradex Apalis iMX6Q on Apalis Evaluation Board";
++ compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q",
"fsl,imx6q";
++};
+diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+new file mode 100644
+index 0000000..cf1ef48
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+@@ -0,0 +1,25 @@
++/*
++ * Copyright 2014-2015 Toradex AG
++ * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++#include "imx6q.dtsi"
++#include "imx6qdl-apalis.dtsi"
++#include "imx6qdl-apalis-ixora.dtsi"
++
++/ {
++ model = "Toradex Apalis iMX6Q on Apalis Ixora Board";
++ compatible = "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q",
"fsl,imx6q";
++};
+diff --git a/arch/arm/boot/dts/imx6q-apalis_v1_0-eval.dts
b/arch/arm/boot/dts/imx6q-apalis_v1_0-eval.dts
+new file mode 100644
+index 0000000..bdf8ac32
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6q-apalis_v1_0-eval.dts
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014-2015 Toradex AG
++ * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++#include "imx6q.dtsi"
++/* on HW V1.0 all RxD/TxD lines are routed in a DCE way, all control lines
(RTS/...)
++ are then not routed as given in the module specification and thus unusable.
++ The following define configures the UARTs to RxD/TxD correctly */
++#define USE_UART_IN_DCE_MODE
++#include "imx6qdl-apalis.dtsi"
++#include "imx6qdl-apalis-eval.dtsi"
++
++/ {
++ model = "Toradex Apalis iMX6Q on Apalis Evaluation Board";
++ compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q",
"fsl,imx6q";
++};
+diff --git a/arch/arm/boot/dts/imx6q-apalis_v1_0-ixora.dts
b/arch/arm/boot/dts/imx6q-apalis_v1_0-ixora.dts
+new file mode 100644
+index 0000000..1c5ca79
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6q-apalis_v1_0-ixora.dts
+@@ -0,0 +1,29 @@
++/*
++ * Copyright 2014-2015 Toradex AG
++ * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++#include "imx6q.dtsi"
++/* on HW V1.0 all RxD/TxD lines are routed in a DCE way, all control lines
(RTS/...)
++ are then not routed as given in the module specification and thus unusable.
++ The following define configures the UARTs to RxD/TxD correctly */
++#define USE_UART_IN_DCE_MODE
++#include "imx6qdl-apalis.dtsi"
++#include "imx6qdl-apalis-ixora.dtsi"
++
++/ {
++ model = "Toradex Apalis iMX6Q on Apalis Ixora Board v1.0";
++ compatible = "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q",
"fsl,imx6q";
++};
+diff --git a/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi
b/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi
+new file mode 100644
+index 0000000..a2d8e51
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi
+@@ -0,0 +1,357 @@
++/*
++ * Copyright 2014-2015 Toradex AG
++ * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++ aliases {
++ i2c0 = &i2cddc;
++ i2c1 = &i2c1;
++ i2c2 = &i2c2;
++ i2c3 = &i2c3;
++ };
++
++ aliases {
++ /* the following, together with kernel patches, forces a fixed
assignment
++ between device id and usdhc controller */
++ /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */
++ mmc0 = &usdhc3; /* eMMC */
++ mmc1 = &usdhc1; /* MMC1 8bit slot */
++ mmc2 = &usdhc2; /* SD1 4bit slot */
++ };
++
++ aliases {
++ rtc0 = &rtc_i2c;
++ rtc1 = "/soc/aips-bus@02000000/snvs@020cc000/snvs-rtc-lp@34";
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_keys>;
++
++ wakeup {
++ label = "Wake-Up";
++ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_WAKEUP>;
++ debounce-interval = <10>;
++ gpio-key,wakeup;
++ };
++ };
++
++ pwmleds {
++ compatible = "pwm-leds";
++ ledpwm1 {
++ label = "PWM1";
++ pwms = <&pwm1 0 50000>;
++ max-brightness = <255>;
++ };
++
++ ledpwm2 {
++ label = "PWM2";
++ pwms = <&pwm2 0 50000>;
++ max-brightness = <255>;
++ };
++
++ ledpwm3 {
++ label = "PWM3";
++ pwms = <&pwm3 0 50000>;
++ max-brightness = <255>;
++ };
++ };
++
++ regulators {
++ reg_usb_otg_vbus: usb_otg_vbus {
++ status = "okay";
++ };
++
++ reg_usb_host_vbus: usb_host_vbus {
++ status = "okay";
++ };
++ };
++
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_cap_1 { // second parallel camera
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <1>;
++ csi_id = <1>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_cap_2 { // mipi-csi2 camera
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <1>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++#if 0
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++#endif
++};
++
++&mipi_csi {
++ ipu_id = <0>;
++ csi_id = <1>;
++ v_channel = <0>;
++ lanes = <2>;
++ status = "okay";
++};
++
++&backlight {
++#if 0 /* PWM polarity: if 1 is brightest */
++#if 0 /* Fusion 7 needs 10kHz PWM frequency */
++ pwms = <&pwm4 0 100000>;
++#endif
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++#else /* PWM plarity: if 0 is brightest */
++ brightness-levels = <0 127 191 223 239 247 251 255>;
++ default-brightness-level = <1>;
++#endif
++ status = "okay";
++};
++
++/* Apalis SPI1 */
++&ecspi1 {
++ status = "okay";
++
++ spidev0: spidev@1 {
++ compatible = "spidev";
++ reg = <0>;
++ spi-max-frequency = <50000000>;
++ };
++};
++
++/* Apalis SPI2 */
++&ecspi2 {
++ status = "okay";
++
++ spidev1: spidev@2 {
++ compatible = "spidev";
++ reg = <0>;
++ spi-max-frequency = <50000000>;
++ };
++};
++
++&can1 {
++ status = "okay";
++};
++
++&can2 {
++ status = "okay";
++};
++
++/*
++ * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
++ * board)
++ */
++&i2c1 {
++ status = "okay";
++
++ pcap@10 {
++ /* TouchRevolution Fusion 7 and 10 multi-touch controller */
++ compatible = "touchrevolution,fusion-f0710a";
++ reg = <0x10>;
++ gpios = <&gpio6 10 0 /* MXM3 11, Pen down interrupt */
++ &gpio6 9 0 /* MXM3 13, Reset */
++ >;
++ };
++
++ pcie-switch@58 {
++ compatible = "plx,pex8605";
++ reg = <0x58>;
++ };
++
++ /* M41T0M6 real time clock on carrier board */
++ rtc_i2c: rtc@68 {
++ compatible = "st,m41t00";
++ reg = <0x68>;
++ };
++};
++
++/*
++ * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
++ */
++&i2c3 {
++ status = "okay";
++
++ /* Video ADC on Analog Camera Module */
++ adv7180: adv7180@21 {
++ compatible = "adv,adv7180";
++ reg = <0x21>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
++ clocks = <&clks 200>;
++ clock-names = "csi_mclk";
++ DOVDD-supply = <®_3p3v>; /* 3.3v */
++ AVDD-supply = <®_3p3v>; /* 1.8v */
++ DVDD-supply = <®_3p3v>; /* 1.8v */
++ PVDD-supply = <®_3p3v>; /* 1.8v */
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <1>;
++ cvbs = <1>;
++ };
++
++ max9526: max9526@20 {
++ compatible = "maxim,max9526";
++ reg = <0x20>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
++ clocks = <&clks 200>;
++ clock-names = "csi_mclk";
++ DVDDIO-supply = <®_3p3v>; /* 3.3v */
++ AVDD-supply = <®_3p3v>; /* 1.8v */
++ DVDD-supply = <®_3p3v>; /* 1.8v */
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <1>;
++ cvbs = <1>;
++ };
++
++ ov5640_mipi@3c {
++ compatible = "ovti,ov5640_mipi";
++ reg = <0x3c>;
++ clocks = <&clks 147>;
++ clock-names = "csi_mclk";
++ DOVDD-supply = <®_1p8v>;
++ AVDD-supply = <®_2p5v>;
++ DVDD-supply = <®_1p8v>;
++ pwn-gpios = <&gpio6 9 1>;
++ rst-gpios = <&gpio2 5 0>;
++ ipu_id = <0>;
++ csi_id = <1>;
++ mclk = <22000000>;
++ mclk_source = <0>;
++ pwms = <&pwm3 0 45>;
++ };
++};
++
++&iomuxc {
++ /*
++ * Mux the Apalis GPIOs, GPIO7 used for PCIe reset,
++ * GPIO5, 6 used by optional fusion_F0710A kernel module
++ */
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
++ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
++ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
++ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8>;
++};
++
++&lcd {
++ status = "okay";
++};
++
++&mxcfb1 {
++ status = "okay";
++};
++
++&mxcfb2 {
++ status = "okay";
++};
++
++&mxcfb3 {
++ status = "okay";
++};
++
++&mxcfb4 {
++ status = "okay";
++};
++
++&pcie {
++ reset-gpio = <&gpio1 2 0>;
++ reset-ep-gpio = <&gpio1 28 0>;
++ status = "okay";
++};
++
++&pwm1 {
++ status = "okay";
++};
++
++&pwm2 {
++ status = "okay";
++};
++
++&pwm3 {
++ status = "okay";
++};
++
++&pwm4 {
++ status = "okay";
++};
++
++&sata {
++ status = "okay";
++};
++
++&sound_spdif {
++ status = "okay";
++};
++
++&spdif {
++ status = "okay";
++};
++
++&uart1 {
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++#if 0
++ linux,rs485-enabled-at-boot-time;
++#endif
++};
++
++&uart4 {
++ status = "okay";
++};
++
++&uart5 {
++ status = "okay";
++};
++
++&usbh1 {
++ status = "okay";
++};
++
++&usbotg {
++ status = "okay";
++};
++
++/* MMC1 */
++&usdhc1 {
++ status = "okay";
++};
++
++/* SD1 */
++&usdhc2 {
++ status = "okay";
++};
++
++&vdac {
++ status = "okay";
++};
+diff --git a/arch/arm/boot/dts/imx6qdl-apalis-ixora.dtsi
b/arch/arm/boot/dts/imx6qdl-apalis-ixora.dtsi
+new file mode 100644
+index 0000000..22f0f36
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6qdl-apalis-ixora.dtsi
+@@ -0,0 +1,333 @@
++/*
++ * Copyright 2014-2015 Toradex AG
++ * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++ aliases {
++ i2c0 = &i2cddc;
++ i2c1 = &i2c1;
++ i2c2 = &i2c2;
++ i2c3 = &i2c3;
++ };
++
++ aliases {
++ /* the following, together with kernel patches, forces a fixed
assignment
++ between device id and usdhc controller */
++ /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */
++ mmc0 = &usdhc3; /* eMMC */
++ mmc2 = &usdhc2; /* SD1 4bit slot */
++ };
++
++ aliases {
++ rtc0 = &rtc_i2c;
++ rtc1 = "/soc/aips-bus@02000000/snvs@020cc000/snvs-rtc-lp@34";
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_keys>;
++
++ wakeup {
++ label = "Wake-Up";
++ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_WAKEUP>;
++ debounce-interval = <10>;
++ gpio-key,wakeup;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_leds_ixora>;
++
++ led4-green {
++ label = "LED_4_GREEN";
++ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
++ };
++
++ led4-red {
++ label = "LED_4_RED";
++ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
++ };
++
++ led5-green {
++ label = "LED_5_GREEN";
++ gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
++ };
++
++ led5-red {
++ label = "LED_5_RED";
++ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ pwmleds {
++ compatible = "pwm-leds";
++ ledpwm1 {
++ label = "PWM1";
++ pwms = <&pwm1 0 50000>;
++ max-brightness = <255>;
++ };
++
++ ledpwm2 {
++ label = "PWM2";
++ pwms = <&pwm2 0 50000>;
++ max-brightness = <255>;
++ };
++
++ ledpwm3 {
++ label = "PWM3";
++ pwms = <&pwm3 0 50000>;
++ max-brightness = <255>;
++ };
++ };
++
++ regulators {
++ reg_usb_otg_vbus: usb_otg_vbus {
++ status = "okay";
++ };
++
++ reg_usb_host_vbus: usb_host_vbus {
++ status = "okay";
++ };
++ };
++
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++#if 0
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++#endif
++};
++
++&backlight {
++#if 0 /* PWM polarity: if 1 is brightest */
++#if 0 /* Fusion 7 needs 10kHz PWM frequency */
++ pwms = <&pwm4 0 100000>;
++#endif
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++#else /* PWM plarity: if 0 is brightest */
++ brightness-levels = <0 127 191 223 239 247 251 255>;
++ default-brightness-level = <1>;
++#endif
++ status = "okay";
++};
++
++/* Apalis SPI1 */
++&ecspi1 {
++ status = "okay";
++
++ spidev0: spidev@1 {
++ compatible = "spidev";
++ reg = <0>;
++ spi-max-frequency = <50000000>;
++ };
++};
++
++&can1 {
++ status = "okay";
++};
++
++&can2 {
++ status = "okay";
++};
++
++/*
++ * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
++ * board)
++ */
++&i2c1 {
++ status = "okay";
++
++ pcap@10 {
++ /* TouchRevolution Fusion 7 and 10 multi-touch controller */
++ compatible = "touchrevolution,fusion-f0710a";
++ reg = <0x10>;
++ gpios = <&gpio6 10 0 /* MXM3 11, Pen down interrupt */
++ &gpio6 9 0 /* MXM3 13, Reset */
++ >;
++ };
++
++ cat24c02@50 {
++ compatible = "atmel,24c02";
++ reg = <0x50>;
++ };
++
++ /* M41T0M6 real time clock on carrier board */
++ rtc_i2c: rtc@68 {
++ compatible = "st,m41t00";
++ reg = <0x68>;
++ };
++};
++
++/*
++ * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
++ */
++&i2c3 {
++ status = "okay";
++
++ /* Video ADC on Analog Camera Module */
++ adv7180: adv7180@21 {
++ compatible = "adv,adv7180";
++ reg = <0x21>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
++ clocks = <&clks 200>;
++ clock-names = "csi_mclk";
++ DOVDD-supply = <®_3p3v>; /* 3.3v */
++ AVDD-supply = <®_3p3v>; /* 1.8v */
++ DVDD-supply = <®_3p3v>; /* 1.8v */
++ PVDD-supply = <®_3p3v>; /* 1.8v */
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <1>;
++ cvbs = <1>;
++ };
++
++ max9526: max9526@20 {
++ compatible = "maxim,max9526";
++ reg = <0x20>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
++ clocks = <&clks 200>;
++ clock-names = "csi_mclk";
++ DVDDIO-supply = <®_3p3v>; /* 3.3v */
++ AVDD-supply = <®_3p3v>; /* 1.8v */
++ DVDD-supply = <®_3p3v>; /* 1.8v */
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <1>;
++ cvbs = <1>;
++ };
++};
++
++&iomuxc {
++ /*
++ * Mux the Apalis GPIOs, GPIO7 used for PCIe reset,
++ * GPIO5, 6 used by optional fusion_F0710A kernel module
++ */
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
++ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
++ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
++ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8>;
++
++ leds_ixora {
++ pinctrl_leds_ixora: leds-ixora {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 PAD_CTRL_HYS_PU
++ MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 PAD_CTRL_HYS_PU
++ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 PAD_CTRL_HYS_PU
++ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 PAD_CTRL_HYS_PU
++ >;
++ };
++ };
++};
++
++&lcd {
++ status = "okay";
++};
++
++&mxcfb1 {
++ status = "okay";
++};
++
++&mxcfb2 {
++ status = "okay";
++};
++
++&mxcfb3 {
++ status = "okay";
++};
++
++&mxcfb4 {
++ status = "okay";
++};
++
++&pcie {
++ reset-ep-gpio = <&gpio1 28 0>;
++ status = "okay";
++};
++
++&pwm1 {
++ status = "okay";
++};
++
++&pwm2 {
++ status = "okay";
++};
++
++&pwm3 {
++ status = "okay";
++};
++
++&pwm4 {
++ status = "okay";
++};
++
++&sata {
++ status = "okay";
++};
++
++&sound_spdif {
++ status = "okay";
++};
++
++&spdif {
++ status = "okay";
++};
++
++&uart1 {
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++#if 0
++ linux,rs485-enabled-at-boot-time;
++#endif
++};
++
++&uart4 {
++ status = "okay";
++};
++
++&uart5 {
++ status = "okay";
++};
++
++&usbh1 {
++ status = "okay";
++};
++
++&usbotg {
++ status = "okay";
++};
++
++/* SD1 */
++&usdhc2 {
++ status = "okay";
++};
+diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+new file mode 100644
+index 0000000..778afed
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+@@ -0,0 +1,1107 @@
++/*
++ * Copyright 2014-2015 Toradex AG
++ * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/ {
++ model = "Toradex Apalis iMX6Q Module";
++ compatible = "toradex,apalis_imx6q", "fsl,imx6q";
++
++ aliases {
++ mxcfb0 = &mxcfb1;
++ mxcfb1 = &mxcfb2;
++ mxcfb2 = &mxcfb3;
++ mxcfb3 = &mxcfb4;
++ };
++
++ backlight: backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm4 0 5000000>;
++ status = "disabled";
++ };
++
++ clocks {
++ clk24m: clk24m {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <24000000>;
++ };
++ };
++
++/*
++ * DDC_I2C: I2C2_SDA/SCL on MXM3 205/207
++ */
++ i2cddc: i2c@0 {
++ compatible = "i2c-gpio";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c_ddc>;
++ gpios = <&gpio3 16 0 /* sda */
++ &gpio2 30 0 /* scl */
++ >;
++ i2c-gpio,delay-us = <2>; /* ~100 kHz */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++ };
++
++ lcd: lcd@0 {
++ compatible = "fsl,lcd";
++ ipu_id = <0>;
++ disp_id = <1>;
++ default_ifmt = "RGB24";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_lcdif>;
++ status = "disabled";
++ };
++
++ memory {
++ /* This node is rewritten by U-Boot with the actual memory size
*/
++ reg = <0x10000000 0x80000000>;
++ };
++
++#if 0
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "mipi_dsi";
++ interface_pix_fmt = "RGB666";
++ mode_str ="LDB-XGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++#else
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "LVDS666";
++ mode_str ="LDB-XGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++#endif
++ };
++
++ mxcfb2: fb@1 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb3: fb@2 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "lcd";
++ interface_pix_fmt = "RGB565";
++ mode_str ="CLAA-WVGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++#if 0
++ mxcfb4: fb@3 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ mode_str ="LDB-XGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++#else
++ mxcfb4: fb@3 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "vdac";
++ interface_pix_fmt = "RGB565";
++ mode_str ="LDB-XGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++#endif
++
++ regulators {
++ compatible = "simple-bus";
++
++ reg_1p8v: 1p8v {
++ compatible = "regulator-fixed";
++ regulator-name = "1P8V";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ };
++
++ reg_2p5v: 2p5v {
++ compatible = "regulator-fixed";
++ regulator-name = "2P5V";
++ regulator-min-microvolt = <2500000>;
++ regulator-max-microvolt = <2500000>;
++ regulator-always-on;
++ };
++
++ reg_3p3v: 3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_usb_otg_vbus: usb_otg_vbus {
++ compatible = "regulator-fixed";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio3 22 0>;
++ enable-active-high;
++ status = "disabled";
++ };
++
++ /* on module usb hub */
++ reg_usb_host_vbus_hub: usb_host_vbus_hub {
++ compatible = "regulator-fixed";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
++ regulator-name = "usb_host_vbus_hub";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio3 28 0>;
++ startup-delay-us = <2000>;
++ enable-active-high;
++ status = "okay";
++ };
++
++ reg_usb_host_vbus: usb_host_vbus {
++ compatible = "regulator-fixed";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
++ regulator-name = "usb_host_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio1 0 0>;
++ enable-active-high;
++ vin-supply = <®_usb_host_vbus_hub>;
++ status = "disabled";
++ };
++ };
++
++ sound {
++ compatible = "fsl,imx6q-apalis-sgtl5000",
++ "fsl,imx-audio-sgtl5000";
++ model = "imx6q-apalis-sgtl5000";
++ cpu-dai = <&ssi1>;
++ audio-codec = <&codec>;
++ audio-routing =
++ "MIC_IN", "Mic Jack",
++ "Mic Jack", "Mic Bias",
++ "Headphone Jack", "HP_OUT";
++ mux-int-port = <1>;
++ mux-ext-port = <4>;
++ };
++
++ sound_spdif: sound-spdif {
++ compatible = "fsl,imx-audio-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-out;
++ spdif-in;
++ status = "disabled";
++ };
++
++ vdac: vdac@0 {
++ compatible = "fsl,vdac";
++ ipu_id = <1>;
++ disp_id = <0>;
++ default_ifmt = "RGB565";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu2_vdac>;
++ status = "disabled";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++};
++
++&audmux {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux &pinctrl_audmux_mclk>;
++ status = "okay";
++};
++
++/* Apalis SPI1 */
++&ecspi1 {
++ fsl,spi-num-chipselects = <1>;
++ cs-gpios = <&gpio5 25 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_spi_cs1>;
++ status = "disabled";
++};
++
++/* Apalis SPI2 */
++&ecspi2 {
++ fsl,spi-num-chipselects = <1>;
++ cs-gpios = <&gpio2 26 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_spi_cs2>;
++ status = "disabled";
++};
++
++&fec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet &pinctrl_enet_ctrl>;
++ phy-mode = "rgmii";
++ /*phy-reset-gpios = <&gpio1 25 0>;*/
++ status = "okay";
++
++ #address-cells = <0>;
++ #size-cells = <1>;
++ phy_int {
++ reg = <0x6>;
++ interrupt-parent = <&gpio1>;
++ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
++ };
++};
++
++&can1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan1>;
++ status = "disabled";
++};
++
++&can2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan2>;
++ status = "disabled";
++};
++
++/*
++ * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
++ * board)
++ */
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1>;
++ status = "disabled";
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2>;
++ status = "okay";
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze100";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++ };
++ };
++
++ codec: sgtl5000@0a {
++ compatible = "fsl,sgtl5000";
++ reg = <0x0a>;
++ clocks = <&clks 201>;
++ VDDA-supply = <®_2p5v>;
++ VDDIO-supply = <®_3p3v>;
++ };
++
++ /* STMPE811 touch screen controller */
++ stmpe811@41 {
++ compatible = "st,stmpe811";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_touch_int>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x41>;
++ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio4>;
++ interrupt-controller;
++ id = <0>;
++ blocks = <0x5>;
++ irq-trigger = <0x1>;
++ stmpe_touchscreen {
++ compatible = "st,stmpe-ts";
++ reg = <0>;
++ /* 3.25 MHz ADC clock speed */
++ st,adc-freq = <1>;
++ /* 8 sample average control */
++ st,ave-ctrl = <3>;
++ /* 7 length fractional part in z */
++ st,fraction-z = <7>;
++ /*
++ * 50 mA typical 80 mA max touchscreen drivers
++ * current limit value
++ */
++ st,i-drive = <1>;
++ /* 12-bit ADC */
++ st,mod-12b = <1>;
++ /* internal ADC reference */
++ st,ref-sel = <0>;
++ /* ADC converstion time: 80 clocks */
++ st,sample-time = <4>;
++ /* 1 ms panel driver settling time */
++ st,settling = <3>;
++ /* 5 ms touch detect interrupt delay */
++ st,touch-det-delay = <5>;
++ };
++ stmpe_adc {
++ compatible = "st,stmpe-adc";
++ /* 3.25 MHz ADC clock speed */
++ st,adc-freq = <1>;
++ /* 12-bit ADC */
++ st,mod-12b = <1>;
++ /* internal ADC reference */
++ st,ref-sel = <0>;
++ /* ADC converstion time: 80 clocks */
++ st,sample-time = <4>;
++ };
++ };
++};
++
++/*
++ * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
++ */
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default", "recovery";
++ pinctrl-0 = <&pinctrl_i2c3>;
++ pinctrl-1 = <&pinctrl_i2c3_recovery>;
++ gpios = <&gpio3 18 0 /* sda */
++ &gpio3 17 0 /* scl */
++ >;
++ status = "disabled";
++};
++
++/* PAD Ctrl Values for Common Settings */
++#define PAD_CTRL_HYS_PU 0x1b0b0 /*(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |
PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/
++#define PAD_CTRL_HYS_PD 0x130b0 /*(PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PKE |
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/
++#define PAD_CTRL_PU_22k 0x0f058 /*(PAD_CTL_PUS_22K_UP | PAD_CTL_PUE |
PAD_CTL_PKE | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm)*/
++#define PAD_CTRL_NO 0x80000000
++
++&iomuxc {
++ ecspi {
++ pinctrl_ecspi1: ecspi1grp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
++ MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
++ MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
++ >;
++ };
++ pinctrl_ecspi2: ecspi2grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
++ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
++ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
++ >;
++ };
++ pinctrl_spi_cs1: spi_cs1 {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25
PAD_CTRL_NO /* SPI1 cs */
++ >;
++ };
++ pinctrl_spi_cs2: spi_cs2 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_RW__GPIO2_IO26
PAD_CTRL_NO /* SPI2 cs */
++ >;
++ };
++ };
++
++ flexcan {
++ pinctrl_flexcan1: flexcan1grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
++ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000
++ >;
++ };
++ pinctrl_flexcan2: flexcan2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
++ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
++ >;
++ };
++ };
++
++ gpio {
++ pinctrl_apalis_gpio1: apalis_gpio1 {
++ fsl,pins = <
++ /* Apalis GPIO */
++ MX6QDL_PAD_NANDF_D4__GPIO2_IO04
PAD_CTRL_HYS_PD /* Apalis GPIO1 */
++ >;
++ };
++ pinctrl_apalis_gpio2: apalis_gpio2 {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_D5__GPIO2_IO05
PAD_CTRL_HYS_PD /* Apalis GPIO2 */
++ >;
++ };
++ pinctrl_apalis_gpio3: apalis_gpio3 {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_D6__GPIO2_IO06
PAD_CTRL_HYS_PD /* Apalis GPIO3 */
++ >;
++ };
++ pinctrl_apalis_gpio4: apalis_gpio4 {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_D7__GPIO2_IO07
PAD_CTRL_HYS_PD /* Apalis GPIO4 */
++ >;
++ };
++ pinctrl_apalis_gpio5: apalis_gpio5 {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10
PAD_CTRL_HYS_PD /* Apalis GPIO5 */
++ >;
++ };
++ pinctrl_apalis_gpio6: apalis_gpio6 {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09
PAD_CTRL_HYS_PD /* Apalis GPIO6 */
++ >;
++ };
++ pinctrl_apalis_gpio7: apalis_gpio7 {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_2__GPIO1_IO02
PAD_CTRL_HYS_PD /* Apalis GPIO7 */
++ >;
++ };
++ pinctrl_apalis_gpio8: apalis_gpio8 {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_6__GPIO1_IO06
PAD_CTRL_HYS_PD /* Apalis GPIO8 */
++ >;
++ };
++ pinctrl_gpio_keys: gpio_keys {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04
PAD_CTRL_HYS_PU /* Power Button */
++ >;
++ };
++ };
++
++ hdmi {
++ pinctrl_hdmi_cec: hdmicecgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
++ >;
++ };
++ };
++
++ i2c {
++ pinctrl_i2c_ddc: i2c_ddc {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_EB2__GPIO2_IO30
PAD_CTRL_HYS_PU /* DDC bitbang */
++ MX6QDL_PAD_EIM_D16__GPIO3_IO16
PAD_CTRL_HYS_PU /* DDC bitbang */
++ >;
++ };
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
++ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
++ >;
++ };
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
++ >;
++ };
++ pinctrl_i2c3_recovery: i2c3-recoverygrp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
++ MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
++ >;
++ };
++ };
++
++ /* pins used on module */
++ imx6q-apalis {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_reset_moci &pinctrl_emmc_reset>;
++ pinctrl_audmux: audmuxgrp {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
++ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
++ MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
++ MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
++ >;
++ };
++ pinctrl_audmux_mclk: audmux_mclk {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x000b0
/* SGTL5000 sys_mclk */
++ >;
++ };
++ pinctrl_emmc_reset: emmc_reset {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_RST__GPIO7_IO08
PAD_CTRL_PU_22k /* eMMC reset, leave it alone */
++ >;
++ };
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ >;
++ };
++ pinctrl_enet_ctrl: enet_ctrlgrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25
PAD_CTRL_NO /* ENET phy reset */
++ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30
PAD_CTRL_HYS_PU /* ENET phy interrupt */
++ >;
++ };
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++ pinctrl_ipu2_vdac: ipu2vdacgrp {
++ fsl,pins = <
++ MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xD1
++ MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xD1
++ MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xD1
++ MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xD1
++ MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xF9
++ MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xF9
++ MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xF9
++ MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xF9
++ MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xF9
++ MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xF9
++ MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xF9
++ MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xF9
++ MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xF9
++ MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xF9
++ MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xF9
++ MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xF9
++ MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xF9
++ MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xF9
++ MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xF9
++ MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xF9
++ >;
++ };
++ pinctrl_regulator_usbhub_pwr: gpio_regulator_usbhub_pwr {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D28__GPIO3_IO28
PAD_CTRL_PU_22k /* USBH_HUB_EN */
++ >;
++ };
++ pinctrl_reset_moci: gpio_reset_moci {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28
PAD_CTRL_PU_22k /* RESET_MOCI control */
++ >;
++ };
++ pinctrl_touch_int: touch_intgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL2__GPIO4_IO10
PAD_CTRL_HYS_PU /* STMPE811 interrupt */
++ >;
++ };
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
++ >;
++ };
++ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { /* 100Mhz */
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170B9
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170B9
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170B9
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170B9
++ >;
++ };
++ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { /* 200Mhz */
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170F9
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170F9
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170F9
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170F9
++ >;
++ };
++ };
++
++ ipu1 {
++ pinctrl_ipu1_lcdif: ipu1lcdifgrp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61
++ MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61
/* DE */
++ MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61
/* HSync */
++ MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61
/* VSync */
++ MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61
++ MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61
++ MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61
++ MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61
++ MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61
++ MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61
++ MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61
++ MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61
++ MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61
++ MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61
++ MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61
++ MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61
++ MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61
++ MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61
++ MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61
++ MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61
++ MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61
++ MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61
++ MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61
++ MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61
++ MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61
++ MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61
++ MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61
++ MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61
++ >;
++ };
++ pinctrl_cam_mclk: cam_mclk {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
/* CAM sys_mclk */
++ >;
++ };
++ pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12
0xb0b1
++ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13
0xb0b1
++ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14
0xb0b1
++ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15
0xb0b1
++ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16
0xb0b1
++ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17
0xb0b1
++ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18
0xb0b1
++ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19
0xb0b1
++ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK
0xb0b1
++ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC
0xb0b1
++ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC
0xb0b1
++ >;
++ };
++ };
++
++ pwm {
++ pinctrl_pwm1: pwm1grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
++ >;
++ };
++ pinctrl_pwm2: pwm2grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
++ >;
++ };
++ pinctrl_pwm3: pwm3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
++ >;
++ };
++ pinctrl_pwm4: pwm4grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
++ >;
++ };
++ };
++
++ spdif {
++ pinctrl_spdif: spdifgrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
++ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
++ >;
++ };
++ };
++
++ uart1 {
++ pinctrl_uart1_dce: uart1-dcegrp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
++ >;
++ };
++ pinctrl_uart1_dte: uart1-dtegrp { /* DTE mode */
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
++ MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
++ >;
++ };
++ pinctrl_uart1_ctrl: uart1-ctrlgrp { /* Additional DTR, DSR, DCD
*/
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
++ MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
++ MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
++ >;
++ };
++ };
++
++ uart2 {
++ pinctrl_uart2_dce: uart2-dcegrp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
++ >;
++ };
++ pinctrl_uart2_dte: uart2grp-dte { /* DTE mode */
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
++ MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
++ >;
++ };
++ };
++
++ uart4 {
++ pinctrl_uart4_dce: uart4-dcegrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
++ >;
++ };
++ pinctrl_uart4_dte: uart4-dtegrp { /* DTE mode */
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
++ >;
++ };
++ };
++
++ uart5 {
++ pinctrl_uart5_dce: uart5-dcegrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
++ >;
++ };
++ pinctrl_uart5_dte: uart5-dtegrp { /* DTE mode */
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
++ >;
++ };
++ };
++
++ usbh {
++ pinctrl_regulator_usbh_pwr: gpio_regulator_usbh_pwr {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_0__GPIO1_IO00
PAD_CTRL_PU_22k /* USBH_EN */
++ >;
++ };
++ };
++
++ usbotg {
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
++ >;
++ };
++ pinctrl_regulator_usbotg_pwr: gpio_regulator_usbotg_pwr {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D22__GPIO3_IO22
PAD_CTRL_PU_22k /* USBO power en */
++ >;
++ };
++ };
++
++ usdhc {
++ pinctrl_mmc_cd: gpio_mmc_cd {
++ fsl,pins = <
++ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20
PAD_CTRL_NO /* MMC1 CD */
++ >;
++ };
++ pinctrl_sd_cd: gpio_sd_cd {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14
PAD_CTRL_NO /* SD1 CD */
++ >;
++ };
++ pinctrl_usdhc1: usdhc1grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
++ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
++ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
++ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
++ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
++ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
++ MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
++ MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
++ MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
++ MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
++ >;
++ };
++ pinctrl_usdhc2: usdhc2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++ >;
++ };
++ };
++};
++
++&ldb {
++ ipu_id = <1>;
++ disp_id = <1>;
++ ext_ref = <1>;
++ mode = "spl1";
++ sec_ipu_id = <1>;
++ sec_disp_id = <0>;
++ status = "okay";
++};
++
++&pwm1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm1>;
++ status = "disabled";
++};
++
++&pwm2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm2>;
++ status = "disabled";
++};
++
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm3>;
++ status = "disabled";
++};
++
++&pwm4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm4>;
++ status = "disabled";
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_spdif>;
++ status = "disabled";
++};
++
++&ssi1 {
++ fsl,mode = "i2s-slave";
++ status = "okay";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++#ifndef USE_UART_IN_DCE_MODE
++ pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
++ fsl,dte-mode;
++ fsl,uart-has-rtscts;
++#else
++ pinctrl-0 = <&pinctrl_uart1_dce>;
++#endif
++ status = "disabled";
++};
++
++&uart2 {
++ pinctrl-names = "default";
++#ifndef USE_UART_IN_DCE_MODE
++ pinctrl-0 = <&pinctrl_uart2_dte>;
++ fsl,dte-mode;
++ fsl,uart-has-rtscts;
++#else
++ pinctrl-0 = <&pinctrl_uart2_dce>;
++#endif
++ status = "disabled";
++};
++
++&uart4 {
++ pinctrl-names = "default";
++#ifndef USE_UART_IN_DCE_MODE
++ pinctrl-0 = <&pinctrl_uart4_dte>;
++ fsl,dte-mode;
++#else
++ pinctrl-0 = <&pinctrl_uart4_dce>;
++#endif
++ status = "disabled";
++};
++
++&uart5 {
++ pinctrl-names = "default";
++#ifndef USE_UART_IN_DCE_MODE
++ pinctrl-0 = <&pinctrl_uart5_dte>;
++ fsl,dte-mode;
++#else
++ pinctrl-0 = <&pinctrl_uart5_dce>;
++#endif
++ status = "disabled";
++};
++
++&usbh1 {
++ vbus-supply = <®_usb_host_vbus>;
++ status = "disabled";
++};
++
++&usbotg {
++ vbus-supply = <®_usb_otg_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg>;
++ disable-over-current;
++ status = "disabled";
++};
++
++/* MMC1 */
++&usdhc1 {
++ label = "MMC1";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
++ cd-gpios = <&gpio4 20 0>;
++ vmmc-supply = <®_3p3v>;
++ bus-width = <8>;
++ no-1-8-v;
++ status = "disabled";
++};
++
++/* SD1 */
++&usdhc2 {
++ label = "SD1";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
++ cd-gpios = <&gpio6 14 0>;
++ vmmc-supply = <®_3p3v>;
++ bus-width = <4>;
++ no-1-8-v;
++ status = "disabled";
++};
++
++/* eMMC */
++&usdhc3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ vmmc-supply = <®_3p3v>;
++ bus-width = <8>;
++ no-1-8-v;
++ non-removable;
++ status = "okay";
++};
++
++&weim {
++ status = "disabled"; /* weim signals not accessible on i.MX6 */
++};
+--
+1.7.9.5
+
diff --git
a/target/linux/imx6/patches-4.1/300-pcie-imx6-add-reset-function-for-reseting-downstream.patch
b/target/linux/imx6/patches-4.1/300-pcie-imx6-add-reset-function-for-reseting-downstream.patch
new file mode 100644
index 0000000..c1bbaa8
--- /dev/null
+++
b/target/linux/imx6/patches-4.1/300-pcie-imx6-add-reset-function-for-reseting-downstream.patch
@@ -0,0 +1,79 @@
+From 37f31601d32cfec48c0b69bc6e08f2aff08d4c6a Mon Sep 17 00:00:00 2001
+From: Max Krummenacher <max.krummenac...@toradex.com>
+Date: Fri, 21 Nov 2014 18:58:02 +0100
+Subject: [PATCH 2/3] pcie-imx6: add reset function for reseting downstream EP
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+With the following dtb node one can define a gpio to reset
+downstream endpoints.
+reset-ep-gpio = <...>;
+Currently the logic is 1 for reset asserted
+and 0 for reset deasserted.
+
+Some pcie switches require their downstream endpoints to be kept in reset
+for an additonal millisecond after their reset has been deasserted.
+(cherry picked from commit 94a60e7f645965b1e422e4e80aa8ccb9e0ec845c)
+
+Conflicts:
+
+ drivers/pci/host/pci-imx6.c
+
+Signed-off-by: Petr Štetiar <yn...@true.cz>
+---
+ drivers/pci/host/pci-imx6.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
+index fdb9536..904165b 100644
+--- a/drivers/pci/host/pci-imx6.c
++++ b/drivers/pci/host/pci-imx6.c
+@@ -36,6 +36,7 @@ struct imx6_pcie {
+ struct clk *pcie_bus;
+ struct clk *pcie_phy;
+ struct clk *pcie;
++ int reset_ep_gpio;
+ struct pcie_port pp;
+ struct regmap *iomuxc_gpr;
+ void __iomem *mem_base;
+@@ -293,9 +294,18 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port
*pp)
+
+ /* Some boards don't have PCIe reset GPIO. */
+ if (gpio_is_valid(imx6_pcie->reset_gpio)) {
++ if (gpio_is_valid(imx6_pcie->reset_ep_gpio))
++ gpio_set_value(imx6_pcie->reset_ep_gpio, 1);
+ gpio_set_value(imx6_pcie->reset_gpio, 0);
+ msleep(100);
+ gpio_set_value(imx6_pcie->reset_gpio, 1);
++ msleep(1);
++ if (gpio_is_valid(imx6_pcie->reset_ep_gpio))
++ gpio_set_value(imx6_pcie->reset_ep_gpio, 0);
++ } else if (gpio_is_valid(imx6_pcie->reset_ep_gpio)) {
++ gpio_set_value(imx6_pcie->reset_ep_gpio, 1);
++ msleep(100);
++ gpio_set_value(imx6_pcie->reset_ep_gpio, 0);
+ }
+ return 0;
+
+@@ -587,6 +597,17 @@ static int __init imx6_pcie_probe(struct platform_device
*pdev)
+ return ret;
+ }
+ }
++ imx6_pcie->reset_ep_gpio = of_get_named_gpio(np, "reset-ep-gpio", 0);
++ if (gpio_is_valid(imx6_pcie->reset_ep_gpio)) {
++ ret = devm_gpio_request_one(&pdev->dev,
++ imx6_pcie->reset_ep_gpio,
++ GPIOF_OUT_INIT_HIGH,
++ "PCIe EP reset");
++ if (ret) {
++ dev_err(&pdev->dev, "unable to get reset end point
gpio\n");
++ return ret;
++ }
++ }
+
+ /* Fetch clocks */
+ imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
+--
+1.7.9.5
+
diff --git a/target/linux/imx6/profiles/130-toradex.mk
b/target/linux/imx6/profiles/130-toradex.mk
new file mode 100644
index 0000000..45cf4ac
--- /dev/null
+++ b/target/linux/imx6/profiles/130-toradex.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2015 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Profile/APALIS
+ NAME:=Toradex Apalis family
+ PACKAGES:= \
+ kmod-thermal-imx kmod-usb-chipidea-imx kmod-usb-mxs-phy \
+ kmod-can kmod-can-flexcan kmod-can-raw \
+ kmod-leds-gpio kmod-pps-gpio \
+ kobs-ng
+endef
+
+define Profile/APALIS/Description
+ The Toradex Apalis family of products are based on the Freescale i.MX6
Quad/DualLite SoCs
+endef
+
+APALIS_DTS:= \
+ imx6q-apalis-eval \
+ imx6q-apalis_v1_0-eval \
+ imx6q-apalis-ixora \
+ imx6q-apalis_v1_0-ixora
+
+$(eval $(call Profile,APALIS))
--
1.7.9.5
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