Hi,
comments inline,
On 22/09/2015 15:26, Michael Lee wrote:
> From: michael lee <igv...@gmail.com>
>
> spi clock is the same as system clock measured by logic analyzer.
>
> Signed-off-by: Michael Lee <igv...@gmail.com>
> ---
> .../0012-MIPS-ralink-add-MT7621-support.patch | 29
> +++++++++++++++++-----
> 1 file changed, 23 insertions(+), 6 deletions(-)
>
> diff --git
> a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
> b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
> index 23d3268..bb4a8e1 100644
> ---
> a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
> +++
> b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
> @@ -520,7 +520,7 @@ Signed-off-by: John Crispin <blo...@openwrt.org>
> +}
> --- /dev/null
> +++ b/arch/mips/ralink/mt7621.c
> -@@ -0,0 +1,209 @@
> +@@ -0,0 +1,226 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published
> @@ -553,6 +553,8 @@ Signed-off-by: John Crispin <blo...@openwrt.org>
> +#define SYSC_REG_CUR_CLK_STS 0x44
> +#define CPU_CLK_SEL (BIT(30) | BIT(31))
> +
> ++#define MEMC_REG_BASE 0x5000
> ++
> +#define MT7621_GPIO_MODE_UART1 1
> +#define MT7621_GPIO_MODE_I2C 2
> +#define MT7621_GPIO_MODE_UART3_MASK 0x3
> @@ -645,7 +647,7 @@ Signed-off-by: John Crispin <blo...@openwrt.org>
> + int fbdiv = 0;
> + u32 clk_sts, syscfg;
> + u8 clk_sel = 0, xtal_mode;
> -+ u32 cpu_clk;
> ++ u32 cpu_clk, sys_clk;
> +
> + if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
> + clk_sel = 1;
> @@ -656,24 +658,39 @@ Signed-off-by: John Crispin <blo...@openwrt.org>
> + cpu_fdiv = ((clk_sts >> 8) & 0x1F);
> + cpu_ffrac = (clk_sts & 0x1F);
> + cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
> ++ if (((clk_sts >> 16) & 0x7) == 3)
> ++ sys_clk = cpu_clk / 3;
> ++ else
> ++ sys_clk = cpu_clk / 4;
> + break;
> +
> + case 1:
> -+ fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
> ++ fbdiv = ((rt_sysc_r32(MEMC_REG_BASE + 0x648) >> 4) & 0x7F) + 1;
> + syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
> + xtal_mode = (syscfg >> 6) & 0x7;
> + if(xtal_mode >= 6) { //25Mhz Xtal
> + cpu_clk = 25 * fbdiv * 1000 * 1000;
> + } else if(xtal_mode >=3) { //40Mhz Xtal
> -+ cpu_clk = 40 * fbdiv * 1000 * 1000;
> ++ cpu_clk = 20 * fbdiv * 1000 * 1000;
this looks wrong. can you confirm that this is intentional and not a typo ?
> + } else { // 20Mhz Xtal
> + cpu_clk = 20 * fbdiv * 1000 * 1000;
> + }
> ++ if (syscfg & BIT(5))
> ++ sys_clk = cpu_clk / 4;
> ++ else
> ++ sys_clk = cpu_clk / 3;
> + break;
> + }
> -+ cpu_clk = 880000000;
> ++
> ++#define RFMT(label) label ":%u.%03uMHz "
> ++#define RINT(x) ((x) / 1000000)
> ++#define RFRAC(x) (((x) / 1000) % 1000)
> ++ pr_debug(RFMT("CPU") RFMT("SYS"),
> ++ RINT(cpu_clk), RFRAC(cpu_clk),
> ++ RINT(sys_clk), RFRAC(sys_clk));
> ++
> + ralink_clk_add("cpu", cpu_clk);
> -+ ralink_clk_add("1e000b00.spi", 50000000);
> ++ ralink_clk_add("1e000b00.spi", sys_clk);
> + ralink_clk_add("1e000c00.uartlite", 50000000);
> + ralink_clk_add("1e000d00.uart", 50000000);
> +}
>
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