Scratch this, this is suppose to be in a patch file in
./target/linux/ar71xx/patches-4.1/, will rebase later.
On Thu, Sep 17, 2015 at 7:30 AM, Chris Blake <chrisrblak...@gmail.com>
wrote:
> This patch is to add support for qca955x_eth_rx_delay to work with the
> qca955x SoC.
>
> Signed-off-by: Chris R Blake <chrisrblak...@gmail.com>
>
> ---
> --- a/arch/mips/ath79/dev-eth.c
> +++ b/arch/mips/ath79/dev-eth.c
> @@ -823,6 +825,32 @@
> iounmap(base);
> }
>
> +void __init ath79_setup_qca955x_eth_rx_delay(unsigned int rxd,
> + unsigned int rxdv)
> +{
> + void __iomem *base;
> + u32 t;
> +
> + rxd &= QCA955X_ETH_CFG_RXD_DELAY_MASK;
> + rxdv &= QCA955X_ETH_CFG_RDV_DELAY_MASK;
> +
> + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
> +
> + t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
> +
> + t &= ~(QCA955X_ETH_CFG_RXD_DELAY_MASK << QCA955X_ETH_CFG_RXD_DELAY_SHIFT
> |
> + QCA955X_ETH_CFG_RDV_DELAY_MASK << QCA955X_ETH_CFG_RDV_DELAY_SHIFT);
> +
> + t |= (rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT |
> + rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT);
> +
> + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
> + /* flush write */
> + __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
> +
> + iounmap(base);
> +}
> +
> static int ath79_eth_instance __initdata;
> void __init ath79_register_eth(unsigned int id)
> {
> --- a/arch/mips/ath79/dev-eth.h
> +++ b/arch/mips/ath79/dev-eth.h
> @@ -49,5 +49,6 @@
> void ath79_setup_ar934x_eth_cfg(u32 mask);
> void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
> void ath79_setup_qca955x_eth_cfg(u32 mask);
> +void ath79_setup_qca955x_eth_rx_delay(unsigned int rxd, unsigned int
> rxdv);
>
> #endif /* _ATH79_DEV_ETH_H */
> --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
> +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
> @@ -1098,5 +1098,11 @@
>
> #define QCA955X_ETH_CFG_RGMII_EN BIT(0)
> #define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
> +#define QCA955X_ETH_CFG_RXD_DELAY BIT(14)
> +#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
> +#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
> +#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
> +#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
> +#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
>
> #endif /* __ASM_MACH_AR71XX_REGS_H */
>
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