Hi David, I tested on 2011UiAS-2HnD and 2011UAS-2HnD, and for me, this works better with pll_1000 set to 0x6f000000. But I have to make more testing.
I will conitnue testing... Thanks On Tue, Dec 23, 2014 at 1:57 PM, David Hutchison <dhutchi...@bluemesh.net> wrote: > Hello, > > Can you try: ath79_eth0_pll_data.pll_1000 = 0x6f0000000; > > This is the value I originally found on the 951G, I tried to toggle as > many bits as possible and narrow down from there. John Crispin found > some documentation and we narrowed it down to 0x3e000000 for the 951G. > He is actually working on a patch that will grab the correct > ath79_eth0_pll_data.pll_1000 value from the bootloader. That way this > becomes dynamic. I do not know the progress he has made on it. > > http://comments.gmane.org/gmane.comp.embedded.openwrt.devel/28589 > > Here is our original thread, where John posted the relevant datasheet. > You can take the same approach we did, and narrow down to find your > correct bits. > > It may also be easier to wait for his patch where he will dynamically set > it. > > Hope this helps, > > -- Davey > > On Tue, Dec 23, 2014 at 11:23 AM, Matt Lee <mattlee2...@gmail.com> wrote: > > Hi Chris, > > > >>This patch is the same as the Routerboard 951G fix, I've built this > >>and tested it on my rb-2011uias-2hnd. However we should check that it > >>also works on other/older RB2011 routers which did work OK with the > >>unpatched code. > >> > >>diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c > >>b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c > >>index b73fae6..951ab94 100644 > >>--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c > >>+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c > >>@@ -270,6 +270,7 @@ static int __init rb2011_setup(u32 flags) > >> rb2011_nand_init(); > >> > >> ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | > >>+ AR934X_ETH_CFG_RXD_DELAY | > >> AR934X_ETH_CFG_SW_ONLY_MODE); > >> > >> ath79_register_mdio(1, 0x0); > >>@@ -283,7 +284,7 @@ static int __init rb2011_setup(u32 flags) > >> ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; > >> ath79_eth0_data.phy_mask = BIT(0); > >> ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; > >>- ath79_eth0_pll_data.pll_1000 = 0x06000000; > >>+ ath79_eth0_pll_data.pll_1000 = 0x3e000000; > >> > >> ath79_register_eth(0); > >> > >>-- > >>Chris Green > > This patch is not working correctly for me on the 2011UiAS-2HnD. Many > > packets are dropped, and I can see many FCS Errors and RxBadByte. > > > > root@OpenWrt:/# swconfig dev ag71xx-mdio.0 port 0 show > > Port 0: > > mib: Port 0 MIB counters > > RxBroad : 8 > > RxPause : 0 > > RxMulti : 15 > > RxFcsErr : 800 > > RxAlignErr : 0 > > RxRunt : 0 > > RxFragment : 0 > > Rx64Byte : 7 > > Rx128Byte : 17323 > > Rx256Byte : 6 > > Rx512Byte : 9 > > Rx1024Byte : 0 > > Rx1518Byte : 0 > > RxMaxByte : 0 > > RxTooLong : 0 > > RxGoodByte : 1145334 > > RxBadByte : 65266 > > RxOverFlow : 0 > > Filtered : 11 > > TxBroad : 244 > > TxPause : 0 > > TxMulti : 170 > > TxUnderRun : 0 > > Tx64Byte : 21 > > Tx128Byte : 360 > > Tx256Byte : 20 > > Tx512Byte : 44 > > Tx1024Byte : 14459 > > Tx1518Byte : 3 > > TxMaxByte : 5683 > > TxOverSize : 0 > > TxByte : 16836688 > > TxCollision : 0 > > TxAbortCol : 0 > > TxMultiCol : 0 > > TxSingleCol : 0 > > TxExcDefer : 0 > > TxDefer : 0 > > TxLateCol : 0 > > pvid: 0 > > link: port:0 link:up speed:1000baseT full-duplex txflow rxflow > > > > How can we determine the right value for the > ath79_eth0_pll_data.pll_1000 ? > > > > -matt > > > > > > _______________________________________________ > > openwrt-devel mailing list > > openwrt-devel@lists.openwrt.org > > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel > > >
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