On Wed, Dec 10, 2014 at 04:25:08PM +0100, John Crispin wrote: > > ath79_eth0_pll_data.pll_1000 = 0x6f000000; > > > > Fixes my rb-2011uias-2hnd as well. I now have all ten ethernet > > ports working, the 5 x 10/100 *and* the 5 x Gigabit. > > > > Thanks very much David. > > > > ... and I look forward to a patch with the proper value. > > > > Can test etc. as needed. I even have a faster machine I'm just > > starting to configure as my desktop Linux box (where I do the > > build) so it won't take me so long to build. > > > > > the register layout is as follows for the top 8 bit > > 31 TX_INVERT - Decides whether to select the inversion of the GTX > clock after the delay line > 30 GIGE_QUAD - Decides whether to allow a 2 ns shift (clock in the > middle of a data transfer) to the GTX clock. This bit is only > effective when bit 25 is set. > 29:28 RX_DELAY - The delay buffers in the Rx clock path to adjust > against the edge/middle- aligned RGMII inputs > 27:26 TX_DELAY - Delay line for the GTX clock that goes along with the > data > 25 GIGE - Set only after a 1000 Mbps connection has been negotiated > 24 OFFSET_PHASE - Used to select if the start is from the positive or > negative phase (or whether to have a 180 degree change in addition to > the phase-delay in [11:8]. > > can you try to see if only setting the bits 29:26 is enough or if any > of the other bits need to be set ? if that does not work it has to be > 30, 25 or 24 > I'm away from home now (just got to test the 0x6f000000 before I left) I'll be home on Friday evening and will test fewer bits then.
-- Chris Green _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
