On AR71xx the reset of each module uses such a sequence: ath79_device_reset_set(module_bit); <delay 1> ath79_device_reset_clear(module_bit); <delay 2>
Seems like the reset bits are not self-clearing and polling for the reset to be finished is not possible. Is there any Atheros documentation of the per-module reset timing available? (Or are the required delays just based on trial & error?) At least in the Atheros reference manuals I found nothing. Thanks, Heiner _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
