On Tue, Apr 16, 2013 at 6:32 PM, Drasko DRASKOVIC
<drasko.drasko...@gmail.com> wrote:
> Hi Jon,
> both RT3050 and RT5350 have MIPS 24Kc core. I have successfully used
> OpenOCD with similar (not exactly these) chips, having the same MIPS
> core.
>
> You should use MIPS 4K as a target.
I've bricked one of my AsiaRF modules and I'm trying to recover it.
For some reason reads over my JTAG are painfully slow. Writes as quick.
Takes 20 seconds....
mdw 0x80000198 200
Instant...
mww 0x80000198 200 0
Because reads are terribly broken it take 15 minutes to load uboot
into RAM since OpenOCD verifies the write.
Any idea why reads are so slow?
source [find interface/olimex-arm-usb-ocd.cfg]
set _CHIPNAME rt5350
set _ENDIAN little
set _CPUTAPID 0x1535024f
#daemon configuration
telnet_port 4444
gdb_port 3333
#jtag_speed
adapter_khz 2000
adapter_nsrst_delay 100
jtag_ntrst_delay 100
# jtag scan chain
# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x3
-expected-id $_CPUTAPID
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position
$_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x80080000 -work-area-size 4096
$_TARGETNAME configure -event reset-init {
#reset
halt
echo "init SDRAM controller.."
mww 0x10000300 0xd1825282
mww 0x10000304 0xe0120300
# load_image /home/apps/u-boot/u-boot.bin 0x80000000 bin
# resume 0x80000000
}
reset_config trst_and_srst
>
> At the time I used it extensively I tried to demystify a code that was
> there and the code I contributed, so I crafted a doc that you can
> refer to if you are stuck : http://openocd.zylin.com/#/c/904/ (I am
> sending you a link to the patchset, although it should be merged in
> the main tree. However, I do not see it there :
> http://openocd.git.sourceforge.net/git/gitweb.cgi?p=openocd/openocd;a=tree;f=doc/manual;h=8a9121ca13b9286d258a420f4e301b84bad287b7;hb=08ddb19fd3a708d21057c88e8b86215e04c781ec)
>
> Anyway, I can confirm that I was capable to load and JTAG debug both
> low-level code and Linux, having FASTWRITE and I even added
> coprocessor manipulations from command line (I added this for correct
> cache handling, so now both soft and hard breaks should work fine).
>
> I am very interested to see how this Chinese TOPLINK story develops.
> Please keep us informed.
I have the Toplink boards, but I am not so convinced that Toplink
wants to be in the module business.
I also have the AsiaRF AWM002. AsiaRF is much more interested is
getting OpenWRT going on their stuff.
http://www.asiarf.com/Smallest-Tiny-Ralink-802-11n-Wireless-AP-Router-Module-Board-AWM002-product-view-375.html
With 32MB/8MB the modules are around $8.50 Q1000. AsiaRF will sell Q1
for $15 and a dev carrier board for $30. Dev board exposes JTAG, both
UARTS, two Ethernet and USB.
>
> BR,
> Drasko
>
>
> On Tue, Apr 16, 2013 at 11:05 PM, jonsm...@gmail.com <jonsm...@gmail.com>
> wrote:
>> Does OpenOCD work right on the MIPS core in the RT3050/5350?
>> Does anyone have a script for initializing DRAM so that I can load in a
>> uboot binary?
>>
>> I should be able to:
>> 1) use JTAG to init DRAM
>> 2) copy in the uboot
>> 3) run it
>> 4) use it to write itself to flash
>>
>> I'm waiting for my hardware to come from China.
>>
>> --
>> Jon Smirl
>> jonsm...@gmail.com
>>
>> _______________________________________________
>> openwrt-devel mailing list
>> openwrt-devel@lists.openwrt.org
>> https://lists.openwrt.org/mailman/listinfo/openwrt-devel
>>
> _______________________________________________
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--
Jon Smirl
jonsm...@gmail.com
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