Add support for Qualcomm Atheros QCA9556 SoC and the AP132 Reference Board.
Tested-by: Embedded Wireless GmbH www.embeddedwireless.de
Signed-off-by: Embedded Wireless GmbH <info at embeddedwireless.de>
---
Index: target/linux/ar71xx/files/arch/mips/ath79/mach-ap132.c
===================================================================
--- target/linux/ar71xx/files/arch/mips/ath79/mach-ap132.c (revision 0)
+++ target/linux/ar71xx/files/arch/mips/ath79/mach-ap132.c (revision 0)
@@ -0,0 +1,189 @@
+/*
+ * Atheros AP132 reference board support
+ *
+ * Copyright (c) 2012 Qualcomm Atheros
+ * Copyright (c) 2012 Gabor Juhos <juh...@openwrt.org>
+ * Copyright (c) 2013 Embedded Wireless GmbH <i...@embeddedwireless.de>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/ar8216_platform.h>
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "common.h"
+#include "dev-ap9x-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-eth.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define AP132_GPIO_LED_USB 4
+#define AP132_GPIO_LED_WLAN_5G 12
+#define AP132_GPIO_LED_WLAN_2G 13
+#define AP132_GPIO_LED_STATUS_RED 14
+#define AP132_GPIO_LED_WPS_RED 15
+
+#define AP132_GPIO_BTN_WPS 16
+
+#define AP132_KEYS_POLL_INTERVAL 20 /* msecs */
+#define AP132_KEYS_DEBOUNCE_INTERVAL (3 * AP132_KEYS_POLL_INTERVAL)
+
+#define AP132_MAC0_OFFSET 0
+#define AP132_WMAC_CALDATA_OFFSET 0x1000
+
+static struct gpio_led ap132_leds_gpio[] __initdata = {
+ {
+ .name = "ap132:red:status",
+ .gpio = AP132_GPIO_LED_STATUS_RED,
+ .active_low = 1,
+ },
+ {
+ .name = "ap132:red:wps",
+ .gpio = AP132_GPIO_LED_WPS_RED,
+ .active_low = 1,
+ },
+ {
+ .name = "ap132:red:wlan-2g",
+ .gpio = AP132_GPIO_LED_WLAN_2G,
+ .active_low = 1,
+ },
+ {
+ .name = "ap132:red:usb",
+ .gpio = AP132_GPIO_LED_USB,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button ap132_gpio_keys[] __initdata = {
+ {
+ .desc = "WPS button",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = AP132_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = AP132_GPIO_BTN_WPS,
+ .active_low = 1,
+ },
+};
+
+static struct ar8327_pad_cfg ap132_ar8327_pad0_cfg;
+
+static struct ar8327_platform_data ap132_ar8327_data = {
+ .pad0_cfg = &ap132_ar8327_pad0_cfg,
+ .port0_cfg = {
+ .force_link = 1,
+ .speed = AR8327_PORT_SPEED_1000,
+ .duplex = 1,
+ .txpause = 1,
+ .rxpause = 1,
+ },
+};
+
+static struct mdio_board_info ap132_mdio1_info[] = {
+ {
+ .bus_id = "ag71xx-mdio.1",
+ .phy_addr = 0,
+ .platform_data = &ap132_ar8327_data,
+ },
+};
+
+static void __init ap132_mdio_setup(void)
+{
+ void __iomem *base;
+ u32 t;
+
+#define GPIO_IN_ENABLE3_ADDRESS 0x0050
+#define GPIO_IN_ENABLE3_MII_GE1_MDI_MASK 0x00ff0000
+#define GPIO_IN_ENABLE3_MII_GE1_MDI_LSB 16
+#define GPIO_IN_ENABLE3_MII_GE1_MDI_SET(x) (((x) <<
GPIO_IN_ENABLE3_MII_GE1_MDI_LSB) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK)
+#define GPIO_OUT_FUNCTION4_ADDRESS 0x003c
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK 0xff000000
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB 24
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(x) (((x) <<
GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK)
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8
+#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) <<
GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK)
+
+ base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
+
+ t = __raw_readl(base + GPIO_IN_ENABLE3_ADDRESS);
+ t &= ~GPIO_IN_ENABLE3_MII_GE1_MDI_MASK;
+ t |= GPIO_IN_ENABLE3_MII_GE1_MDI_SET(19);
+ __raw_writel(t, base + GPIO_IN_ENABLE3_ADDRESS);
+
+
+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 19), base
+ AR71XX_GPIO_REG_OE);
+
+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 17), base
+ AR71XX_GPIO_REG_OE);
+
+
+ t = __raw_readl(base + GPIO_OUT_FUNCTION4_ADDRESS);
+ t &= ~(GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK |
GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK);
+ t |= GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(0x20) |
GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(0x21);
+ __raw_writel(t, base + GPIO_OUT_FUNCTION4_ADDRESS);
+
+ iounmap(base);
+
+}
+
+static void __init ap132_setup(void)
+{
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
+ ath79_register_m25p80(NULL);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap132_leds_gpio),
+ ap132_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, AP132_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(ap132_gpio_keys),
+ ap132_gpio_keys);
+
+ ath79_register_usb();
+
+ ath79_register_wmac(art + AP132_WMAC_CALDATA_OFFSET, NULL);
+
+ /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
+ ap132_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
+ ap132_ar8327_pad0_cfg.sgmii_delay_en = true;
+
+ ath79_eth1_pll_data.pll_1000 = 0x03000101;
+
+ ap132_mdio_setup();
+
+ ath79_register_mdio(1, 0x0);
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, art + AP132_MAC0_OFFSET, 0);
+
+ mdiobus_register_board_info(ap132_mdio1_info,
+ ARRAY_SIZE(ap132_mdio1_info));
+
+ /* GMAC1 is connected to the SGMII interface */
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
+ ath79_eth1_data.speed = SPEED_1000;
+ ath79_eth1_data.duplex = DUPLEX_FULL;
+ ath79_eth1_data.phy_mask = BIT(0);
+ ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
+
+ ath79_register_eth(1);
+}
+
+MIPS_MACHINE(ATH79_MACH_AP132, "AP132",
+ "Atheros AP132 reference board",
+ ap132_setup);
+
Index: target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
===================================================================
--- target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c (revision 35166)
+++ target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c (working copy)
@@ -181,6 +181,7 @@
if (ath79_soc == ATH79_SOC_AR9341 ||
ath79_soc == ATH79_SOC_AR9342 ||
ath79_soc == ATH79_SOC_AR9344 ||
+ ath79_soc == ATH79_SOC_QCA9556 ||
ath79_soc == ATH79_SOC_QCA9558)
max_id = 1;
else
@@ -202,6 +203,7 @@
case ATH79_SOC_AR9341:
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
+ case ATH79_SOC_QCA9556:
case ATH79_SOC_QCA9558:
if (id == 0) {
mdio_dev = &ath79_mdio0_device;
@@ -250,12 +252,17 @@
}
mdio_data->is_ar934x = 1;
break;
+
case ATH79_SOC_QCA9558:
if (id == 1)
mdio_data->builtin_switch = 1;
mdio_data->is_ar934x = 1;
break;
+ case ATH79_SOC_QCA9556:
+ mdio_data->is_ar934x = 1;
+ break;
+
default:
break;
}
@@ -560,6 +567,7 @@
case ATH79_SOC_AR9341:
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
+ case ATH79_SOC_QCA9556:
case ATH79_SOC_QCA9558:
pll_10 = AR934X_PLL_VAL_10;
pll_100 = AR934X_PLL_VAL_100;
@@ -636,6 +644,7 @@
}
break;
+ case ATH79_SOC_QCA9556:
case ATH79_SOC_QCA9558:
switch (pdata->phy_if_mode) {
case PHY_INTERFACE_MODE_MII:
@@ -693,6 +702,7 @@
}
break;
+ case ATH79_SOC_QCA9556:
case ATH79_SOC_QCA9558:
switch (pdata->phy_if_mode) {
case PHY_INTERFACE_MODE_MII:
@@ -953,6 +963,7 @@
pdata->fifo_cfg3 = 0x01f00140;
break;
+ case ATH79_SOC_QCA9556:
case ATH79_SOC_QCA9558:
if (id == 0) {
pdata->reset_bit = QCA955X_RESET_GE0_MAC |
@@ -1018,6 +1029,7 @@
pdata->mii_bus_dev = &ath79_mdio1_device.dev;
break;
+ case ATH79_SOC_QCA9556:
case ATH79_SOC_QCA9558:
/* don't assign any MDIO device by default */
break;
Index: target/linux/ar71xx/image/Makefile
===================================================================
--- target/linux/ar71xx/image/Makefile (revision 35166)
+++ target/linux/ar71xx/image/Makefile (working copy)
@@ -165,6 +165,7 @@
ap113_mtd_layout=mtdparts=spi0.0:64k(u-boot),3008k(rootfs),896k(uImage),64k(NVRAM),64k(ART),3904k@0x10000(firmware)
ap121_mtdlayout_2M=mtdparts=spi0.0:64k(u-boot)ro,1216k(rootfs),704k(kernel),64k(art)ro,1920k@0x10000(firmware)
ap121_mtdlayout_4M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,2752k(rootfs),896k(kernel),64k(nvram),64k(art)ro,3648k@0x50000(firmware)
+ap132_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),6400k(rootfs),64k(art),7808k@0x50000(firmware)
ap135_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,14528k(rootfs),1408k(kernel),64k(mib0),64k(art)ro,7744k@0x50000(firmware)
ap136_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1408k(kernel),64k(mib0),64k(art)ro,7744k@0x50000(firmware)
cameo7240_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(nvram)ro,960k(kernel),2752k(rootfs),64k(mac)ro,64k(art)ro,3712k@0x40000(firmware)
@@ -821,6 +822,7 @@
$(eval $(call
SingleProfile,AthLzma,$(fs_64k),AP121_2M,ap121-2M,AP121,ttyATH0,115200,$$(ap121_mtdlayout_2M),720896,1245184,RKuImage))
$(eval $(call
SingleProfile,AthLzma,$(fs_64k),AP121_4M,ap121-4M,AP121,ttyATH0,115200,$$(ap121_mtdlayout_4M),917504,2818048,RKuImage))
$(eval $(call
SingleProfile,AthLzma,$(fs_64k),AP121MINI,ap121-mini,AP121-MINI,ttyATH0,115200,$$(ap121_mtdlayout_4M),917504,2818048,RKuImage))
+$(eval $(call
SingleProfile,AthLzma,$(fs_64k),AP132,ap132,AP132,ttyS0,115200,$$(ap132_mtdlayout),1441792,6553600,KRuImage))
$(eval $(call
SingleProfile,AthLzma,$(fs_64k),AP135,ap135-020,AP135-020,ttyS0,115200,$$(ap135_mtdlayout),1441792,6488064,RKuImage))
$(eval $(call
SingleProfile,AthLzma,$(fs_64k),AP136_010,ap136-010,AP136-010,ttyS0,115200,$$(ap136_mtdlayout),1441792,6488064,RKuImage))
$(eval $(call
SingleProfile,AthLzma,$(fs_64k),AP136_020,ap136-020,AP136-020,ttyS0,115200,$$(ap136_mtdlayout),1441792,6488064,RKuImage))
Index: target/linux/ar71xx/base-files/lib/ar71xx.sh
===================================================================
--- target/linux/ar71xx/base-files/lib/ar71xx.sh (revision 35166)
+++ target/linux/ar71xx/base-files/lib/ar71xx.sh (working copy)
@@ -174,6 +174,9 @@
*AP121-MINI)
name="ap121-mini"
;;
+ *"AP132 reference board")
+ name="ap132"
+ ;;
*"AP136-010 reference board")
name="ap136-010"
;;
Index: target/linux/ar71xx/base-files/lib/upgrade/platform.sh
===================================================================
--- target/linux/ar71xx/base-files/lib/upgrade/platform.sh (revision 35166)
+++ target/linux/ar71xx/base-files/lib/upgrade/platform.sh (working copy)
@@ -104,6 +104,7 @@
;;
ap81 | \
ap83 | \
+ ap132 | \
dir-600-a1 | \
dir-615-c1 | \
dir-615-e4 | \
Index: target/linux/ar71xx/base-files/etc/uci-defaults/network
===================================================================
--- target/linux/ar71xx/base-files/etc/uci-defaults/network (revision 35166)
+++ target/linux/ar71xx/base-files/etc/uci-defaults/network (working copy)
@@ -22,6 +22,13 @@
ucidef_set_interface_lan "eth0 eth1"
;;
+ap132)
+ ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2"
+ ucidef_add_switch "switch0" "1" "1"
+ ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5"
+ ucidef_add_switch_vlan "switch0" "2" "0t 1"
+ ;;
+
ap136-010)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
ucidef_add_switch "switch0" "1" "1"
Index: target/linux/ar71xx/base-files/etc/diag.sh
===================================================================
--- target/linux/ar71xx/base-files/etc/diag.sh (revision 35166)
+++ target/linux/ar71xx/base-files/etc/diag.sh (working copy)
@@ -36,6 +36,9 @@
all0305)
status_led="eap7660d:green:ds4"
;;
+ ap132)
+ status_led="ap132:green:status"
+ ;;
ap136-010|\
ap136-020)
status_led="ap136:green:status"
Index: target/linux/ar71xx/config-3.7
===================================================================
--- target/linux/ar71xx/config-3.7 (revision 35166)
+++ target/linux/ar71xx/config-3.7 (working copy)
@@ -28,6 +28,7 @@
CONFIG_ATH79_MACH_ALL0315N=y
CONFIG_ATH79_MACH_AP113=y
CONFIG_ATH79_MACH_AP121=y
+CONFIG_ATH79_MACH_AP132=y
CONFIG_ATH79_MACH_AP136=y
CONFIG_ATH79_MACH_AP81=y
CONFIG_ATH79_MACH_AP83=y
Index: target/linux/ar71xx/generic/profiles/atheros.mk
===================================================================
--- target/linux/ar71xx/generic/profiles/atheros.mk (revision 35166)
+++ target/linux/ar71xx/generic/profiles/atheros.mk (working copy)
@@ -38,6 +38,17 @@
$(eval $(call Profile,AP121MINI))
+define Profile/AP132
+ NAME:=Atheros AP132 reference board
+ PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage
+endef
+
+define Profile/AP132/Description
+ Package set optimized for the Atheros AP132 reference board.
+endef
+
+$(eval $(call Profile,AP132))
+
define Profile/AP135
NAME:=Atheros AP135 reference board
PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage
Index:
target/linux/ar71xx/patches-3.7/611-MIPS-ath79-add-QCA9556-SoC-on-AP132.patch
===================================================================
---
target/linux/ar71xx/patches-3.7/611-MIPS-ath79-add-QCA9556-SoC-on-AP132.patch
(revision 0)
+++
target/linux/ar71xx/patches-3.7/611-MIPS-ath79-add-QCA9556-SoC-on-AP132.patch
(revision 0)
@@ -0,0 +1,103 @@
+diff -ur linux_orig/arch/mips/ath79/Kconfig linux/arch/mips/ath79/Kconfig
+--- linux_orig/arch/mips/ath79/Kconfig 2013-01-14 09:51:12.879638000 +0100
++++ linux/arch/mips/ath79/Kconfig 2013-01-14 10:19:02.490794000 +0100
+@@ -70,6 +70,18 @@
+ Say 'Y' here if you want your kernel to support the
+ Atheros AP121 reference board.
+
++config ATH79_MACH_AP132
++ bool "Atheros AP132 reference board"
++ select SOC_QCA955X
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_SPI
++ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
++ help
++ Say 'Y' here if you want your kernel to support the
++ Atheros AP132 reference boards.
++
+ config ATH79_MACH_AP136
+ bool "Atheros AP136/AP135 reference board"
+ select SOC_QCA955X
+diff -ur linux_orig/arch/mips/ath79/machtypes.h
linux/arch/mips/ath79/machtypes.h
+--- linux_orig/arch/mips/ath79/machtypes.h 2013-01-14 09:51:12.879638000
+0100
++++ linux/arch/mips/ath79/machtypes.h 2013-01-14 10:17:44.119813000 +0100
+@@ -24,6 +24,7 @@
+ ATH79_MACH_AP113, /* Atheros AP113 reference board */
+ ATH79_MACH_AP121, /* Atheros AP121 reference board */
+ ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
++ ATH79_MACH_AP132, /* Atheros AP132 reference board */
+ ATH79_MACH_AP135_020, /* Atheros AP135-020 reference board */
+ ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */
+ ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */
+diff -ur linux_orig/arch/mips/ath79/Makefile linux/arch/mips/ath79/Makefile
+--- linux_orig/arch/mips/ath79/Makefile 2013-01-14 09:51:12.879638000
+0100
++++ linux/arch/mips/ath79/Makefile 2013-01-14 10:16:46.971098000 +0100
+@@ -44,6 +44,7 @@
+ obj-$(CONFIG_ATH79_MACH_ALL0315N) += mach-all0315n.o
+ obj-$(CONFIG_ATH79_MACH_AP113) += mach-ap113.o
+ obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
++obj-$(CONFIG_ATH79_MACH_AP132) += mach-ap132.o
+ obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o
+ obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
+ obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o
+diff -ur linux_orig/arch/mips/ath79/setup.c linux/arch/mips/ath79/setup.c
+--- linux_orig/arch/mips/ath79/setup.c 2013-01-14 09:51:12.287423000 +0100
++++ linux/arch/mips/ath79/setup.c 2013-01-14 10:15:13.579034000 +0100
+@@ -164,6 +164,12 @@
+ rev = id & AR934X_REV_ID_REVISION_MASK;
+ break;
+
++ case REV_ID_MAJOR_QCA9556:
++ ath79_soc = ATH79_SOC_QCA9556;
++ chip = "9556";
++ rev = id & AR944X_REV_ID_REVISION_MASK;
++ break;
++
+ case REV_ID_MAJOR_QCA9558:
+ ath79_soc = ATH79_SOC_QCA9558;
+ chip = "9558";
+diff -ur linux_orig/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
linux/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+--- linux_orig/arch/mips/include/asm/mach-ath79/ar71xx_regs.h 2013-01-14
09:51:12.543328000 +0100
++++ linux/arch/mips/include/asm/mach-ath79/ar71xx_regs.h 2013-01-14
10:12:47.123971000 +0100
+@@ -565,6 +565,7 @@
+ #define REV_ID_MAJOR_AR9341 0x0120
+ #define REV_ID_MAJOR_AR9342 0x1120
+ #define REV_ID_MAJOR_AR9344 0x2120
++#define REV_ID_MAJOR_QCA9556 0x0130
+ #define REV_ID_MAJOR_QCA9558 0x1130
+
+ #define AR71XX_REV_ID_MINOR_MASK 0x3
+diff -ur linux_orig/arch/mips/include/asm/mach-ath79/ath79.h
linux/arch/mips/include/asm/mach-ath79/ath79.h
+--- linux_orig/arch/mips/include/asm/mach-ath79/ath79.h 2013-01-14
09:51:12.107283000 +0100
++++ linux/arch/mips/include/asm/mach-ath79/ath79.h 2013-01-14
10:13:45.743826000 +0100
+@@ -32,6 +32,7 @@
+ ATH79_SOC_AR9341,
+ ATH79_SOC_AR9342,
+ ATH79_SOC_AR9344,
++ ATH79_SOC_QCA9556,
+ ATH79_SOC_QCA9558,
+ };
+
+@@ -99,6 +100,11 @@
+ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
+ }
+
++static inline int soc_is_qca9556(void)
++{
++ return ath79_soc == ATH79_SOC_QCA9556;
++}
++
+ static inline int soc_is_qca9558(void)
+ {
+ return ath79_soc == ATH79_SOC_QCA9558;
+@@ -106,7 +112,7 @@
+
+ static inline int soc_is_qca955x(void)
+ {
+- return soc_is_qca9558();
++ return soc_is_qca9556() || soc_is_qca9558();
+ }
+
+ extern void __iomem *ath79_ddr_base;
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