Le 06/01/2013 19:57, Gabor Juhos a écrit :
> 2013.01.05. 14:53 keltezéssel, Michel Stempin írta:
>> Here is the result of the same command on a genuine TL-WR703N with the
>> newest factory firmware "3.14.4 build 120925 rel 33144n" (aka "Ver; 1.7"),
>> thanks to Uncle_Vernon on the forum:
>>
>> U-Boot 1.1.4 (Sep 25 2012 - 09:04:47)
>>
>> AP121 (ar9330) U-boot
>>
>> <...>
>>
>> hornet> md.l 0xb8070000 1
>> b8070000: 00000190 ....
>> hornet>
>
> Ok, this means that the description of the original patch is wrong, because
> the
> patch turns off the PHY_SWAP bit and it leaves the PYH_ADDR_SWAP bit set.
Yes: my original patch description is wrong: older firmwares left both bits
reset, newest firmware sets both bits.
>
> In theory, a simple
>
> ath79_setup_ar933x_phy4_switch(false, false);
>
> line should be enough to make it working, and the
>
> ath79_eth0_data.phy_mask = BIT(0);
>
> line should be dropped from the patch.
But it looks like the default for id 0 in ath79_register_eth(id) is to set bit
4 in mask, which is wrong if we swap PHY 0 and 4, is it?
>
>>
>> I prefered to have this test performed on a stock v1.7 device rather than on
>> my modified v1.6, just in case there is an unexpected hardware change
>> between the 2 versions.
>>
>> So it looks like both PHYs and MACs are swapped in v1.7 U-Boot, while this
>> wasn't the case in previous versions.
>>
>> >From what I understand, it looks like the newest U-Boot is routing the
>> >Ethernet port 4 (the only one that is physically connected) through the
>> >eth1 switch, rather than eth0?
>>
>> I don't see a reason for doing this: does it benefit from the GMII speed
>> over simple MII, or is it to enable the switch QoS capabilities? Do you see
>> any other reason?
>
> No, it makes no sense at all. The GE1 interface is always connected to MAC0 of
> the built-in switch via GMII interface regardless of the state of the
> PHY_SWAP/PHY_ADDR_SWAP bits.
Yes, I agree that GE1 interface is always connected to MAC0 according to AR9331
datasheet figure 2-3.
Here is my understanding, correct me if I am wrong (this is quite possible!):
On TL-WR703, the single physical Ethernet port is always connected to port 4,
like in TL-MR3020/TL-MR3040/TL-MR11U.
If both PHY_SWAP and PYH_ADDR_SWAP are reset as with older firmware, the
physical Ethernet is addressed as PHY4 and is routed directly to the CPU MAC5
through MII interface GE0 and PHY mask should be set to BIT(4).
With newer firmware, both PHY_SWAP and PYH_ADDR_SWAP are set, so the physical
Ethernet is addressed as PHY0 and is routed to the switch MAC1, then MAC0, then
through GMII interface GE1 and PHY mask should be set to BIT(0).
So basically, in older config, the Ethernet is routed directly to CPU's MAC5
using GE0 MII interface, while it is now routed through the switch using GE1
GMII interface. Is it correct?
The exact same patch that I proposed, consisting of the
ath79_setup_ar933x_phy4_switch(false, true);
line and the
ath79_eth0_data.phy_mask = BIT(0);
line is already applied in mach-tl-mr3020.c for TL-MR3020 routers and into
mach-tl-mr11u.c for TL-MR3040/TL-MR11U routers, which have the exact same CPU
and hardware configuration.
As I understand it, this patch restores the connection of external port 4 to
PHY0/MAC5 using the direct GE0 MII interface, and connects PHY4/MAC1 in the
switch.
-Michel
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