Inconsistent ETOP register offsets The register offsets the lantiq etop driver is using are inconsistent. This is hidden when using uboot as it already sets up ETOP and PHY once, but becomes an issue when booting using brnboot, which does no network setup by itself.
The MAC_CFG register is missing the 0x10000 offset from PPE32_BASE. ETOP_CFG and ETOP_IGPLEN seem to have had 0x602/0x608 shifted by 4 instead of multiplied by 4. The following corrections are made: LTQ_ETOP_CFG 0x16020 -> 0x11808 LTQ_ETOP_IGPLEN 0x16080 -> 0x11820 LQ_PPE32_ENET_MAC_CFG 0x1840 -> 0x11840 Also I took the liberty of renaming LQ_PPE32_ENET_MAC_CFG to LTQ_ETOP_MAC_CFG for consistency. ^missing T? The duplicate ETOP_CGEN define replaces PPE32_CGEN. This patch could unearth further issues in the driver on devices using u-boot for booting. For my W502V an additional patch is needed to add initialization that is normally done by u-boot. For reference, see package/uboot-lantiq/files/drivers/net/ifx_etop.h (some register naming is slightly different, but you can see the off by 4 and missing offset of the etop driver compared to this include): #define DANUBE_PPE32_BASE 0xBE180000 #define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4)) #define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) #define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) #define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) #define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) #define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) #define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) #define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) #define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) #define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) #define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) #define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) #define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) #define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) #define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) #define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) #define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) #define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) #define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) #define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) #define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) #define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) #define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) #define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) #define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) Signed-off-by: Tobias Diedrich <ranma+open...@tdiedrich.de> Index: target/linux/lantiq/patches-3.3/0026-etop-register-offsets.patch =================================================================== --- target/linux/lantiq/patches-3.3/0026-etop-register-offsets.patch (revision 0) +++ target/linux/lantiq/patches-3.3/0026-etop-register-offsets.patch (working copy) @@ -0,0 +1,40 @@ +Index: linux-3.3.8/drivers/net/ethernet/lantiq_etop.c +=================================================================== +--- linux-3.3.8.orig/drivers/net/ethernet/lantiq_etop.c 2012-08-04 22:56:06.719593549 +0200 ++++ linux-3.3.8/drivers/net/ethernet/lantiq_etop.c 2012-08-04 22:58:06.135766177 +0200 +@@ -53,14 +53,14 @@ + #define MDIO_REG_OFFSET 0x10 + #define MDIO_VAL_MASK 0xffff + +-#define PPE32_CGEN 0x800 +-#define LQ_PPE32_ENET_MAC_CFG 0x1840 ++#define LTQ_ETOP_MAC_CFG 0x11840 ++#define ETOP_CGEN 0x800 + + #define LTQ_ETOP_ENETS0 0x11850 + #define LTQ_ETOP_MAC_DA0 0x1186C + #define LTQ_ETOP_MAC_DA1 0x11870 +-#define LTQ_ETOP_CFG 0x16020 +-#define LTQ_ETOP_IGPLEN 0x16080 ++#define LTQ_ETOP_CFG 0x11808 ++#define LTQ_ETOP_IGPLEN 0x11820 + + #define MAX_DMA_CHAN 0x8 + #define MAX_DMA_CRC_LEN 0x4 +@@ -71,7 +71,6 @@ + #define ETOP_MII_NORMAL 0xd + #define ETOP_MII_REVERSE 0xe + #define ETOP_PLEN_UNDER 0x40 +-#define ETOP_CGEN 0x800 + #define ETOP_CFG_MII0 0x01 + + #define LTQ_GBIT_MDIO_CTL 0xCC +@@ -362,7 +361,7 @@ + } + + /* enable crc generation */ +- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); ++ ltq_etop_w32(ETOP_CGEN, LTQ_ETOP_MAC_CFG); + + return 0; + } -- Tobias PGP: http://8ef7ddba.uguu.de _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
