Currently, sys_clk/10 is used which is just wrong. cpu_clk/10 would work for systems with 400MHz CPU clock.
Signed-off-by: Daniel Golle <dgo...@allnet.de>
---
target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
index 4a99cf3..9585476 100644
--- a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
@@ -60,7 +60,7 @@ void __init rt305x_clocks_init(void)
break;
}
rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
- rt305x_uart_clk.rate = rt305x_sys_clk.rate / 10;
+ rt305x_uart_clk.rate = 40000000;
rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
} else {
BUG();
--
1.7.11.2
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