Hi,

I flashed OpenWrt r29844 on a TP-Link WR-741NDv2.4 with AR9285rev2 and two 
antennas (one external/one internal pcb). Everything works fine, but it uses 
the internal antenna only for RX and the external for TX, as already described 
here: https://dev.openwrt.org/ticket/7576

Due to the directional external antenna I have to use just a single port for 
both RX and TX. However, options txantenna/rxantenna in /etc/config/wireless 
show no effect at all.

If I am right, the AR9285 is an 1x1 chip and we need classical antenna 
diversity enabled in order to benefit of a second antenna. Though antenna 
diversity is disabled on my device due to EEPROM settings:
        
# cat /sys/kernel/debug/ieee80211/phy0/ath9k/modal_eeprom | grep -i ctl
 Ant. Diversity ctl1 :          8
 Ant. Diversity ctl2 :          9
 
# iw phy phy0 info | grep -i ant
        Available Antennas: TX 0x1 RX 0x1
        Configured Antennas: TX 0x1 RX 0x1
        
Is it a good idea to override the EEPROM setting to enable the classical 
antenna diversity to obtain two available rx antennas and then selecting the 
proper antanna using:

# iw phy phy0 set antenna 1 1

I attached a simple patch to override the EEPROM settings. Should I give it a 
try? Or is it possible to enable diversity without compiling?

Thanks in advance.

- Flo

----------------------------------------------------------------
Postfach fast voll? Jetzt kostenlos E-Mail Adresse @t-online.de sichern und 
endlich Platz für tausende Mails haben.
http://www.t-online.de/email-kostenlos
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -343,6 +343,7 @@ static u32 ath9k_hw_4k_get_eeprom(struct
 	case EEP_MODAL_VER:
 		return pModal->version;
 	case EEP_ANT_DIV_CTL1:
+		return 0x9;
 		return pModal->antdiv_ctl1;
 	case EEP_TXGAIN_TYPE:
 		return pBase->txGainType;
@@ -838,6 +839,8 @@ static void ath9k_hw_4k_set_board_values
 	if (pModal->version >= 3) {
 		ant_div_control1 = pModal->antdiv_ctl1;
 		ant_div_control2 = pModal->antdiv_ctl2;
+		ant_div_control1 = 0x9;
+		ant_div_control2 = 0x9;
 
 		regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 		regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
_______________________________________________
openwrt-devel mailing list
openwrt-devel@lists.openwrt.org
https://lists.openwrt.org/mailman/listinfo/openwrt-devel

Reply via email to