This patch is needed to correctly initialize the ETOP network
hardware when booting with BRN-BOOT instead of u-boot.
Apparently the driver was writing to the wrong registers addresses
for some registers, after fixing it to use same register addresses
u-boot is using it works fine with BRN-BOOT for me.
Also, u-boot is using different values for the MII mode and only
those work for me when I'm using BRN-BOOT.
Note that the MII mode registers is one of the registers where the
address was wrong, so it probably was only working previously
because the hardware already was initialized by u-boot.
Lastly, two additional register intialization writes to
LTQ_ETOP_MDIO_CFG and LQ_PPE32_ENET_MAC_CFG are added
(also taken from u-boot code).
Signed-off-by: Tobias Diedrich <ranma+open...@tdiedrich.de>
Index: target/linux/lantiq/patches/870-etop-without-uboot.patch
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ target/linux/lantiq/patches/870-etop-without-uboot.patch 2012-01-29
18:40:51.554564189 +0100
@@ -0,0 +1,57 @@
+Index: linux-3.1.4/drivers/net/lantiq_etop.c
+===================================================================
+--- linux-3.1.4.orig/drivers/net/lantiq_etop.c 2012-01-23 01:48:26.396126527
+0100
++++ linux-3.1.4/drivers/net/lantiq_etop.c 2012-01-23 22:35:43.054258544
+0100
+@@ -42,6 +42,7 @@
+ #include <xway_dma.h>
+ #include <lantiq_platform.h>
+
++#define LTQ_ETOP_MDIO_CFG 0x11800
+ #define LTQ_ETOP_MDIO 0x11804
+ #define MDIO_REQUEST 0x80000000
+ #define MDIO_READ 0x40000000
+@@ -52,13 +53,13 @@
+ #define MDIO_VAL_MASK 0xffff
+
+ #define PPE32_CGEN 0x800
+-#define LQ_PPE32_ENET_MAC_CFG 0x1840
++#define LQ_PPE32_ENET_MAC_CFG 0x11840
+
+ #define LTQ_ETOP_ENETS0 0x11850
+ #define LTQ_ETOP_MAC_DA0 0x1186C
+ #define LTQ_ETOP_MAC_DA1 0x11870
+-#define LTQ_ETOP_CFG 0x16020
+-#define LTQ_ETOP_IGPLEN 0x16080
++#define LTQ_ETOP_CFG 0x11808
++#define LTQ_ETOP_IGPLEN 0x11820
+
+ #define MAX_DMA_CHAN 0x8
+ #define MAX_DMA_CRC_LEN 0x4
+@@ -66,8 +67,8 @@
+
+ #define ETOP_FTCU BIT(28)
+ #define ETOP_MII_MASK 0xf
+-#define ETOP_MII_NORMAL 0xd
+-#define ETOP_MII_REVERSE 0xe
++#define ETOP_MII_NORMAL 0x8
++#define ETOP_MII_REVERSE 0xa
+ #define ETOP_PLEN_UNDER 0x40
+ #define ETOP_CGEN 0x800
+ #define ETOP_CFG_MII0 0x01
+@@ -317,8 +318,16 @@
+ unsigned int mii_mode = priv->pldata->mii_mode;
+ int i;
+
++ pr_info("%s: %dMbit %s txdma:%d rxdma:%d\n", __func__,
++ ltq_has_gbit() ? 1000 : 100,
++ ltq_is_ase() ? "ase" : "non-ase",
++ LTQ_ETOP_TX_CHANNEL,
++ LTQ_ETOP_RX_CHANNEL);
+ ltq_pmu_enable(PMU_PPE);
+
++ ltq_etop_w32_mask(0x6, 0, LTQ_ETOP_MDIO_CFG);
++ ltq_etop_w32(0x187, LQ_PPE32_ENET_MAC_CFG);
++
+ if (ltq_has_gbit()) {
+ ltq_etop_gbit_init();
+ }
--
Tobias PGP: http://8ef7ddba.uguu.de
_______________________________________________
openwrt-devel mailing list
openwrt-devel@lists.openwrt.org
https://lists.openwrt.org/mailman/listinfo/openwrt-devel
