his patch adds kernel support for the MI424-WR. It's a patch file for
kernel 2.6.26.
I also maintain a wiki page for this router here:
http://wiki.openwrt.org/OpenWrtDocs/Hardware/Actiontec/MI424-WR
Note: I arbitrarily added the 333 prefix. Not clear which number to use.
Signed-off-by: Jose Vasconcellos <jvasco at verizon.net>
Index: target/linux/ixp4xx/patches-2.6.26/333-mi424wr_support.patch
===================================================================
--- target/linux/ixp4xx/patches-2.6.26/333-mi424wr_support.patch
(revision 0)
+++ target/linux/ixp4xx/patches-2.6.26/333-mi424wr_support.patch
(revision 0)
@@ -0,0 +1,585 @@
+--- /dev/null 2008-04-22 17:51:32.000000000 -0400
++++ b/include/asm-arm/arch-ixp4xx/mi424wr.h 2008-07-23
17:50:30.000000000 -0400
+@@ -0,0 +1,147 @@
++/*
++ * include/asm-arm/arch-ixp4xx/mi424wr.h
++ *
++ * Author: Jose Vasconcellos
++ * Copyright (c) 2008 Jose Vasconcellos
++ *
++ * Based on gtwx5715.h by
++ *
++ * Copyright 2004 (c) George T. Joseph
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA.
++ */
++
++#ifndef __ASM_ARCH_HARDWARE_H__
++#error "Do not include this directly, instead #include <asm/hardware.h>"
++#endif
++#include "irqs.h"
++
++#define MI424WR_GPIO0 0
++#define MI424WR_GPIO1 1
++#define MI424WR_GPIO2 2
++#define MI424WR_GPIO3 3
++#define MI424WR_GPIO4 4
++#define MI424WR_GPIO5 5
++#define MI424WR_GPIO6 6
++#define MI424WR_GPIO7 7
++#define MI424WR_GPIO8 8
++#define MI424WR_GPIO9 9
++#define MI424WR_GPIO10 10
++#define MI424WR_GPIO11 11
++#define MI424WR_GPIO12 12
++#define MI424WR_GPIO13 13
++#define MI424WR_GPIO14 14
++
++#define MI424WR_GPIO0_IRQ IRQ_IXP4XX_GPIO0
++#define MI424WR_GPIO1_IRQ IRQ_IXP4XX_GPIO1
++#define MI424WR_GPIO2_IRQ IRQ_IXP4XX_GPIO2
++#define MI424WR_GPIO3_IRQ IRQ_IXP4XX_GPIO3
++#define MI424WR_GPIO4_IRQ IRQ_IXP4XX_GPIO4
++#define MI424WR_GPIO5_IRQ IRQ_IXP4XX_GPIO5
++#define MI424WR_GPIO6_IRQ IRQ_IXP4XX_GPIO6
++#define MI424WR_GPIO7_IRQ IRQ_IXP4XX_GPIO7
++#define MI424WR_GPIO8_IRQ IRQ_IXP4XX_GPIO8
++#define MI424WR_GPIO9_IRQ IRQ_IXP4XX_GPIO9
++#define MI424WR_GPIO10_IRQ IRQ_IXP4XX_GPIO10
++#define MI424WR_GPIO11_IRQ IRQ_IXP4XX_GPIO11
++#define MI424WR_GPIO12_IRQ IRQ_IXP4XX_GPIO12
++#define MI424WR_GPIO13_IRQ IRQ_IXP4XX_SW_INT1
++#define MI424WR_GPIO14_IRQ IRQ_IXP4XX_SW_INT2
++
++/* PCI controller GPIO to IRQ pin mappings
++
++ INTA INTB
++SLOT 0 10 11
++SLOT 1 11 10
++SLOT 2 11 10
++
++*/
++
++#define MI424WR_PCI_SLOT0_DEVID 13
++#define MI424WR_PCI_INTA_GPIO MI424WR_GPIO6
++#define MI424WR_PCI_INTA_IRQ MI424WR_GPIO6_IRQ
++
++#define MI424WR_PCI_SLOT1_DEVID 14
++#define MI424WR_PCI_INTB_GPIO MI424WR_GPIO8
++#define MI424WR_PCI_INTB_IRQ MI424WR_GPIO8_IRQ
++
++#define MI424WR_PCI_SLOT2_DEVID 15
++#define MI424WR_PCI_INTC_GPIO MI424WR_GPIO7
++#define MI424WR_PCI_INTC_IRQ MI424WR_GPIO7_IRQ
++
++#define MI424WR_PCI_SLOT_COUNT 3
++#define MI424WR_PCI_INT_PIN_COUNT 3
++
++/*
++ * GPIO 2,3,4 and 9 are hard wired to the Micrel/Kendin KS8995M Switch
++ * and operate as an SPI type interface. The details of the interface
++ * are available on Kendin/Micrel's web site.
++ */
++
++#define MI424WR_KSSPI_SELECT MI424WR_GPIO9
++#define MI424WR_KSSPI_TXD MI424WR_GPIO4
++#define MI424WR_KSSPI_CLOCK MI424WR_GPIO2
++#define MI424WR_KSSPI_RXD MI424WR_GPIO3
++
++/*
++ * The "reset" button is wired to GPIO 10.
++ * The GPIO is brought "low" when the button is pushed.
++ */
++
++#define MI424WR_BUTTON_GPIO MI424WR_GPIO10
++#define MI424WR_BUTTON_IRQ MI424WR_GPIO10_IRQ
++
++#define MI424WR_MOCA_WAN_LED MI424WR_GPIO11
++
++/* Latch on CS1 - taken from Actiontec's 2.4 source code
++ *
++ * default latch value
++ * 0 - power alarm led (red) 0 (off)
++ * 1 - power led (green) 0 (off)
++ * 2 - wireless led (green) 1 (off)
++ * 3 - no internet led (red) 0 (off)
++ * 4 - internet ok led (green) 0 (off)
++ * 5 - moca LAN 0 (off)
++ * 6 - N/A
++ * 7 - PCI reset 1 (not reset)
++ * 8 - IP phone 1 led (green) 1 (off)
++ * 9 - IP phone 2 led (green) 1 (off)
++ * 10 - VOIP ready led (green) 1 (off)
++ * 11 - PSTN relay 1 control 0 (PSTN)
++ * 12 - PSTN relay 1 control 0 (PSTN)
++ * 13 - N/A
++ * 14 - N/A
++ * 15 - N/A
++ */
++
++#define MI424WR_LATCH_DEFAULT 0x1f84
++
++#define MI424WR_LATCH_ALARM_LED 0x00
++#define MI424WR_LATCH_POWER_LED 0x01
++#define MI424WR_LATCH_WIRELESS_LED 0x02
++#define MI424WR_LATCH_INET_DOWN_LED 0x03
++#define MI424WR_LATCH_INET_OK_LED 0x04
++#define MI424WR_LATCH_MOCA_LAN_LED 0x05
++#define MI424WR_LATCH_WAN_ALARM_LED 0x06
++#define MI424WR_LATCH_PCI_RESET 0x07
++#define MI424WR_LATCH_PHONE1_LED 0x08
++#define MI424WR_LATCH_PHONE2_LED 0x09
++#define MI424WR_LATCH_VOIP_LED 0x10
++#define MI424WR_LATCH_PSTN_RELAY1 0x11
++#define MI424WR_LATCH_PSTN_RELAY2 0x12
++
++/* initialize CS1 to default timings, Intel style, 16-bit bus */
++#define MI424WR_CS1_CONFIG 0x80000002
++
+--- /dev/null 2008-04-22 17:51:32.000000000 -0400
++++ b/arch/arm/mach-ixp4xx/mi424wr-pci.c 2008-07-13
17:25:57.000000000 -0400
+@@ -0,0 +1,78 @@
++/*
++ * arch/arm/mach-ixp4xx/mi424wr-pci.c
++ *
++ * Actiontec MI424WR board-level PCI initialization
++ *
++ * Author: Jose Vasconcellos <[EMAIL PROTECTED]>
++ *
++ * Based on ixdp-pci.c
++ * Copyright (C) 2002 Intel Corporation.
++ * Copyright (C) 2003-2004 MontaVista Software, Inc.
++ *
++ * Maintainer: Jose Vasconcellos <[EMAIL PROTECTED]>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++#include <linux/delay.h>
++
++#include <asm/mach/pci.h>
++#include <asm/irq.h>
++#include <asm/hardware.h>
++#include <asm/mach-types.h>
++#include <asm/arch/mi424wr.h>
++
++void __init mi424wr_pci_preinit(void)
++{
++ set_irq_type(MI424WR_PCI_INTA_IRQ, IRQT_LOW);
++ set_irq_type(MI424WR_PCI_INTB_IRQ, IRQT_LOW);
++ set_irq_type(MI424WR_PCI_INTC_IRQ, IRQT_LOW);
++
++ ixp4xx_pci_preinit();
++}
++
++static int __init mi424wr_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
++{
++ static int irqs[3][2] = {
++ {MI424WR_PCI_INTC_IRQ, MI424WR_PCI_INTA_IRQ}, /* MoCA WAN */
++ {MI424WR_PCI_INTB_IRQ, MI424WR_PCI_INTC_IRQ}, /* Mini-PCI */
++ {MI424WR_PCI_INTA_IRQ, MI424WR_PCI_INTB_IRQ}, /* MoCA LAN */
++ };
++
++ int irq = -1;
++
++ if (slot >= 13 && slot <= 15 &&
++ pin >=1 && pin <=2)
++ irq = irqs[slot - 13][pin - 1];
++
++ printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
++ __func__, slot, pin, irq);
++
++ return irq;
++}
++
++struct hw_pci mi424wr_pci __initdata = {
++ .nr_controllers = 1,
++ .preinit = mi424wr_pci_preinit,
++ .swizzle = pci_std_swizzle,
++ .setup = ixp4xx_setup,
++ .scan = ixp4xx_scan_bus,
++ .map_irq = mi424wr_map_irq,
++};
++
++int __init mi424wr_pci_init(void)
++{
++ if (machine_is_mi424wr())
++ pci_common_init(&mi424wr_pci);
++ return 0;
++}
++
++subsys_initcall(mi424wr_pci_init);
++
+--- /dev/null 2008-04-22 17:51:32.000000000 -0400
++++ b/arch/arm/mach-ixp4xx/mi424wr-setup.c 2008-07-23
21:28:26.000000000 -0400
+@@ -0,0 +1,298 @@
++/*
++ * arch/arm/mach-ixp4xx/mi424wr-setup.c
++ *
++ * Actiontec MI424-WR board setup
++ * Copyright (c) 2008 Jose Vasconcellos
++ *
++ * Based on Gemtek GTWX5715 by
++ * Copyright (C) 2004 George T. Joseph
++ * Derived from Coyote
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA.
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/serial.h>
++#include <linux/tty.h>
++#include <linux/serial_8250.h>
++#include <linux/slab.h>
++
++#include <linux/leds.h>
++#include <linux/spi/spi_gpio.h>
++
++#include <asm/types.h>
++#include <asm/setup.h>
++#include <asm/memory.h>
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/flash.h>
++#include <asm/arch/mi424wr.h>
++#include <asm/io.h>
++
++/*
++ * Xscale UART registers are 32 bits wide with only the least
++ * significant 8 bits having any meaning. From a configuration
++ * perspective, this means 2 things...
++ *
++ * Setting .regshift = 2 so that the standard 16550 registers
++ * line up on every 4th byte.
++ *
++ * Shifting the register start virtual address +3 bytes when
++ * compiled big-endian. Since register writes are done on a
++ * single byte basis, if the shift isn't done the driver will
++ * write the value into the most significant byte of the register,
++ * which is ignored, instead of the least significant.
++ */
++
++#ifdef __ARMEB__
++#define REG_OFFSET 3
++#else
++#define REG_OFFSET 0
++#endif
++
++/*
++ * Only the second or "console" uart is connected on the mi424wr.
++ */
++
++static struct resource mi424wr_uart_resources[] = {
++ {
++ .start = IXP4XX_UART1_BASE_PHYS,
++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = IXP4XX_UART2_BASE_PHYS,
++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
++ .flags = IORESOURCE_MEM,
++ }
++};
++
++
++static struct plat_serial8250_port mi424wr_uart_platform_data[] = {
++ {
++ .mapbase = IXP4XX_UART1_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART1,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ {
++ .mapbase = IXP4XX_UART2_BASE_PHYS,
++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
++ .irq = IRQ_IXP4XX_UART2,
++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
++ .iotype = UPIO_MEM,
++ .regshift = 2,
++ .uartclk = IXP4XX_UART_XTAL,
++ },
++ { },
++};
++
++static struct platform_device mi424wr_uart_device = {
++ .name = "serial8250",
++ .id = PLAT8250_DEV_PLATFORM,
++ .dev = {
++ .platform_data = mi424wr_uart_platform_data,
++ },
++ .num_resources = ARRAY_SIZE(mi424wr_uart_resources),
++ .resource = mi424wr_uart_resources,
++};
++
++static struct flash_platform_data mi424wr_flash_data = {
++ .map_name = "cfi_probe",
++ .width = 2,
++};
++
++static struct resource mi424wr_flash_resource = {
++ .flags = IORESOURCE_MEM,
++};
++
++static struct platform_device mi424wr_flash = {
++ .name = "IXP4XX-Flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &mi424wr_flash_data,
++ },
++ .num_resources = 1,
++ .resource = &mi424wr_flash_resource,
++};
++
++static int mi424wr_spi_boardinfo_setup(struct spi_board_info *bi,
++ struct spi_master *master, void *data)
++{
++
++ strlcpy(bi->modalias, "spi-ks8995", sizeof(bi->modalias));
++
++ bi->max_speed_hz = 5000000 /* Hz */;
++ bi->bus_num = master->bus_num;
++ bi->mode = SPI_MODE_0;
++
++ return 0;
++}
++
++static struct spi_gpio_platform_data mi424wr_spi_bus_data = {
++ .pin_cs = MI424WR_KSSPI_SELECT,
++ .pin_clk = MI424WR_KSSPI_CLOCK,
++ .pin_miso = MI424WR_KSSPI_RXD,
++ .pin_mosi = MI424WR_KSSPI_TXD,
++ .cs_activelow = 1,
++ .no_spi_delay = 1,
++ .boardinfo_setup = mi424wr_spi_boardinfo_setup,
++};
++
++static struct gpio_led mi424wr_gpio_led[] = {
++ {
++ .name = "moca-wan", /* green led */
++ .gpio = MI424WR_MOCA_WAN_LED,
++ .active_low = 0,
++ }
++};
++
++static struct gpio_led_platform_data mi424wr_gpio_leds_data = {
++ .num_leds = 1,
++ .leds = mi424wr_gpio_led,
++};
++
++static struct platform_device mi424wr_gpio_leds = {
++ .name = "leds-gpio",
++ .id = -1,
++ .dev.platform_data = &mi424wr_gpio_leds_data,
++};
++
++static struct latch_led mi424wr_latch_led[] = {
++ {
++ .name = "power-alarm",
++ .bit = MI424WR_LATCH_ALARM_LED,
++ },
++ {
++ .name = "power-ok",
++ .bit = MI424WR_LATCH_POWER_LED,
++ },
++ {
++ .name = "wireless", /* green led */
++ .bit = MI424WR_LATCH_WIRELESS_LED,
++ },
++ {
++ .name = "inet-down", /* red led */
++ .bit = MI424WR_LATCH_INET_DOWN_LED,
++ },
++ {
++ .name = "inet-up", /* green led */
++ .bit = MI424WR_LATCH_INET_OK_LED,
++ },
++ {
++ .name = "moca-lan", /* green led */
++ .bit = MI424WR_LATCH_MOCA_LAN_LED,
++ },
++ {
++ .name = "wan-alarm", /* red led */
++ .bit = MI424WR_LATCH_WAN_ALARM_LED,
++ }
++};
++
++static struct latch_led_platform_data mi424wr_latch_leds_data = {
++ .num_leds = ARRAY_SIZE(mi424wr_latch_led),
++ .leds = mi424wr_latch_led,
++ .mem = 0x51000000,
++};
++
++static struct platform_device mi424wr_latch_leds = {
++ .name = "leds-latch",
++ .id = -1,
++ .dev.platform_data = &mi424wr_latch_leds_data,
++};
++
++static struct platform_device mi424wr_spi_bus = {
++ .name = "spi-gpio",
++ .id = 0,
++ .dev = {
++ .platform_data = &mi424wr_spi_bus_data,
++ },
++};
++
++static struct eth_plat_info mi424wr_npeb_data = {
++ .phy = 17, /* KS8721 */
++ .rxq = 3,
++ .txreadyq = 20,
++ .hwaddr = {0x00, 0x03, 0x47, 0xdf, 0x32, 0xa8}
++};
++
++static struct eth_plat_info mi424wr_npec_data = {
++ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
++ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
++ .rxq = 4,
++ .txreadyq = 21,
++ .hwaddr = {0x00, 0x03, 0x47, 0xdf, 0x32, 0xaa}
++};
++
++static struct platform_device mi424wr_npe_devices[] = {
++ {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEB,
++ .dev.platform_data = &mi424wr_npeb_data,
++ }, {
++ .name = "ixp4xx_eth",
++ .id = IXP4XX_ETH_NPEC,
++ .dev.platform_data = &mi424wr_npec_data,
++ }
++};
++
++static struct platform_device *mi424wr_devices[] __initdata = {
++ &mi424wr_uart_device,
++ &mi424wr_flash,
++ &mi424wr_gpio_leds,
++ &mi424wr_latch_leds,
++ &mi424wr_spi_bus,
++ &mi424wr_npe_devices[0],
++ &mi424wr_npe_devices[1],
++};
++
++static void __init mi424wr_init(void)
++{
++ ixp4xx_sys_init();
++
++ mi424wr_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
++ mi424wr_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1;
++
++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
++ *IXP4XX_EXP_CS1 = MI424WR_CS1_CONFIG;
++
++ gpio_line_config(MI424WR_BUTTON_GPIO, IXP4XX_GPIO_IN);
++
++ gpio_line_config(MI424WR_MOCA_WAN_LED, IXP4XX_GPIO_OUT);
++ gpio_line_set(MI424WR_MOCA_WAN_LED, IXP4XX_GPIO_HIGH);
++
++ platform_add_devices(mi424wr_devices, ARRAY_SIZE(mi424wr_devices));
++}
++
++
++MACHINE_START(MI424WR, "Actiontec MI424WR")
++ /* Maintainer: Jose Vasconcellos */
++ .phys_io = IXP4XX_UART2_BASE_PHYS,
++ .io_pg_offst = ((IXP4XX_UART2_BASE_VIRT) >> 18) & 0xfffc,
++ .map_io = ixp4xx_map_io,
++ .init_irq = ixp4xx_init_irq,
++ .timer = &ixp4xx_timer,
++ .boot_params = 0x0100,
++ .init_machine = mi424wr_init,
++MACHINE_END
++
++
+--- a/arch/arm/mach-ixp4xx/Makefile 2008-07-15 14:20:22.000000000 -0400
++++ b/arch/arm/mach-ixp4xx/Makefile 2008-07-13 17:29:53.000000000 -0400
+@@ -24,6 +24,7 @@
+ obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
+ obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
+ obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o
++obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o
+
+ obj-y += common.o
+
+@@ -46,6 +47,7 @@
+ obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
+ obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
+ obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o
++obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o
+
+ obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
+ obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
+--- a/arch/arm/mach-ixp4xx/Kconfig 2008-07-05 18:53:22.000000000 -0400
++++ b/arch/arm/mach-ixp4xx/Kconfig 2008-07-13 17:28:37.000000000 -0400
+@@ -237,6 +237,13 @@
+ "High Speed" UART is n/c (as far as I can tell)
+ 20 Pin ARM/Xscale JTAG interface on J2
+
++config MACH_MI424WR
++ bool "Actiontec MI424WR"
++ depends on ARCH_IXP4XX
++ select PCI
++ help
++ Add support for the Actiontec MI424-WR.
++
+ comment "IXP4xx Options"
+
+ config DMABOUNCE
+--- a/arch/arm/configs/ixp4xx_defconfig 2008-07-05
18:53:22.000000000 -0400
++++ b/arch/arm/configs/ixp4xx_defconfig 2008-07-13
17:24:39.000000000 -0400
+@@ -172,6 +172,7 @@
+ CONFIG_CPU_IXP46X=y
+ CONFIG_CPU_IXP43X=y
+ CONFIG_MACH_GTWX5715=y
++CONFIG_MACH_MI424WR=y
+
+ #
+ # IXP4xx Options
+--- a/include/asm-arm/arch-ixp4xx/hardware.h 2008-07-22
06:02:08.000000000 -0400
++++ b/include/asm-arm/arch-ixp4xx/hardware.h 2008-07-21
11:43:31.000000000 -0400
+@@ -46,5 +46,6 @@
+ #include "nas100d.h"
+ #include "dsmg600.h"
+ #include "fsg.h"
++#include "mi424wr.h"
+
+ #endif /* _ASM_ARCH_HARDWARE_H */
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