Michael Buesch wrote: > I'm sorry, I cannot tell you what causes this. But I guess, however, > it is some change in the ssb setup code that broke this. > > Here's some more evidence. I scanned the phy register space using get_dbe. Here are the results:
Addr Value 3e0 0x3207 (looks ok) 3e2 0x0 3e4 0x4 3e6 bus err 3e8 0x0 3ea bus err 3ec 0x3f22 3ee bus err 3f0 0x8000 3f2 bus err (not implemented) 3f4 bus err 3f6 0x1 (looks ok) 3f8 bus err 3fa 0x17f (looks ok too) 3fc bus err 3fe 0x3207 It looks like (almost) every other phy register doesn't respond. I put in a large (200us) delay between accesses with no change in behaviour. If it is timing, it must be on the pci bus side of the core. I inspected a diff of a working and non-working ssb, b43 and mips/mm, but didn't see anything that could explain this. I'm obviously missing something and will keep looking. Steve _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org http://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
