This patch allows VLYNQ devices on the DG834Gv1 to be successfully
enabled.
Currently the "__vlynq_enable_device" function attempts to set the VLYNQ
device clock divisor to values from 1 through 8 until a link is
successfully established. On the DG834Gv1 (but not the DG834Gv2),
setting the VLYNQ device clock divisor to 1 (full rate) results in all
further VLYNQ operations failing (including software reset), so the
device is never enabled. This patches changes the function to only
attempt divisors 2 through 8, and hence the device is successfully
enabled.
Signed-off-by: Nick Forbes <[EMAIL PROTECTED]>
---------
--- target/linux/ar7/files/drivers/vlynq/vlynq.c.orig 2007-11-27
21:52:13.000000000 +0000
+++ target/linux/ar7/files/drivers/vlynq/vlynq.c 2007-12-03
10:24:05.000000000 +0000
@@ -374,5 +374,5 @@
/* Only try locally supplied clock, others cause
problems */
vlynq_reg_write(dev->remote->control, 0);
- for (i = vlynq_ldiv1; i <= vlynq_ldiv8; i++) {
+ for (i = vlynq_ldiv2; i <= vlynq_ldiv8; i++) {
vlynq_reg_write(dev->local->control,
VLYNQ_CTRL_CLOCK_INT |
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