This is an automated email from Gerrit.
Attila Kinali (att...@kinali.ch) just uploaded a new patch set to Gerrit, which
you can find at http://openocd.zylin.com/128
-- gerrit
commit afd5a73681eec417ded58a22fbe12336acdb0563
Author: Attila Kinali <att...@kinali.ch>
Date: Thu Oct 27 12:14:55 2011 +0200
* Add flash waitstate support for Atmel SAM3 chips.
* Set default waitstates to 6, to workaround a silicon bug in the SAM3
family
This code has been tested on SAM3U4, SAM3N4 and SAM3N1
based on Change-Id: I477446f9bfb3e910ea3e2414a6e9a75beb14a214
by Jim Norris <u17...@att.net>
Change-Id: I8d360080f6968979ca5e197ad638282cadd18fb7
Signed-off-by: Attila Kinali <att...@kinali.ch>
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index c46829e..b5442e8 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -183,6 +183,7 @@ struct sam3_bank_private {
unsigned bank_number;
uint32_t controller_address;
uint32_t base_address;
+ uint32_t flash_wait_states;
bool present;
unsigned size_bytes;
unsigned nsectors;
@@ -298,6 +299,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 128 * 1024,
.nsectors = 16,
@@ -313,6 +315,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_U,
.controller_address = 0x400e0a00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 128 * 1024,
.nsectors = 16,
@@ -347,6 +350,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 128 * 1024,
.nsectors = 16,
@@ -388,6 +392,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 64 * 1024,
.nsectors = 8,
@@ -436,6 +441,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 128 * 1024,
.nsectors = 16,
@@ -450,6 +456,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_U,
.controller_address = 0x400e0a00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 128 * 1024,
.nsectors = 16,
@@ -484,6 +491,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 128 * 1024,
.nsectors = 16,
@@ -525,6 +533,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_U,
.controller_address = 0x400e0800,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 64 * 1024,
.nsectors = 8,
@@ -561,8 +570,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
-
.controller_address = 0x400e0a00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 256 * 1024,
.nsectors = 32,
@@ -594,8 +603,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
-
.controller_address = 0x400e0a00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 256 * 1024,
.nsectors = 32,
@@ -626,8 +635,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
-
.controller_address = 0x400e0a00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 256 * 1024,
.nsectors = 32,
@@ -658,8 +667,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
-
.controller_address = 0x400e0a00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 128 * 1024,
.nsectors = 16,
@@ -690,8 +699,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
-
.controller_address = 0x400e0a00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 128 * 1024,
.nsectors = 16,
@@ -722,8 +731,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
-
.controller_address = 0x400e0a00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 128 * 1024,
.nsectors = 16,
@@ -754,8 +763,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
-
.controller_address = 0x400e0a00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 64 * 1024,
.nsectors = 8,
@@ -786,8 +795,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
-
.controller_address = 0x400e0a00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 64 * 1024,
.nsectors = 8,
@@ -818,8 +827,8 @@ static const struct sam3_chip_details all_sam3_details[] = {
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
-
.controller_address = 0x400e0a00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 64 * 1024,
.nsectors = 8,
@@ -869,6 +878,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 256 * 1024,
.nsectors = 16,
@@ -917,6 +927,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 256 * 1024,
.nsectors = 16,
@@ -965,6 +976,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 256 * 1024,
.nsectors = 16,
@@ -1013,6 +1025,7 @@ static const struct sam3_chip_details all_sam3_details[]
= {
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 128 * 1024,
.nsectors = 8,
@@ -1061,6 +1074,7 @@ static const struct sam3_chip_details all_sam3_details[]
= {
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 128 * 1024,
.nsectors = 8,
@@ -1109,6 +1123,7 @@ static const struct sam3_chip_details all_sam3_details[]
= {
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 128 * 1024,
.nsectors = 8,
@@ -1157,6 +1172,7 @@ static const struct sam3_chip_details all_sam3_details[]
= {
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 64 * 1024,
.nsectors = 4,
@@ -1205,6 +1221,7 @@ static const struct sam3_chip_details all_sam3_details[]
= {
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 64 * 1024,
.nsectors = 4,
@@ -1253,6 +1270,7 @@ static const struct sam3_chip_details all_sam3_details[]
= {
.bank_number = 0,
.base_address = FLASH_BANK_BASE_N,
.controller_address = 0x400e0A00,
+ .flash_wait_states = 6, // workaround silicon bug
.present = 1,
.size_bytes = 64 * 1024,
.nsectors = 4,
@@ -2391,11 +2409,12 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
switch (bank->base) {
default:
LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or
0x%08x \
- [at91sam3u series] or 0x%08x [at91sam3s series])",
+ [at91sam3u series] or 0x%08x [at91sam3s series] or
0x%08x [at91sam3n series])",
((unsigned int)(bank->base)),
((unsigned int)(FLASH_BANK0_BASE_U)),
((unsigned int)(FLASH_BANK1_BASE_U)),
- ((unsigned int)(FLASH_BANK_BASE_S)));
+ ((unsigned int)(FLASH_BANK_BASE_S)),
+ ((unsigned int)(FLASH_BANK_BASE_N)));
return ERROR_FAIL;
break;
@@ -2413,7 +2432,7 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
pChip->details.bank[1].pBank = bank;
break;
- // at91sam3s series
+ // at91sam3s and at91sam3n series
case FLASH_BANK_BASE_S:
bank->driver_priv = &(pChip->details.bank[0]);
bank->bank_number = 0;
@@ -2771,10 +2790,29 @@ sam3_page_write(struct sam3_bank_private *pPrivate,
unsigned pagenum, uint8_t *b
{
uint32_t adr;
uint32_t status;
+ uint32_t fmr; // EEFC Flash Mode Register
int r;
adr = pagenum * pPrivate->page_size;
adr += (adr + pPrivate->base_address);
+
+ // Get flash mode register value
+ r = target_read_u32(pPrivate->pChip->target,
pPrivate->controller_address, &fmr);
+ if (r != ERROR_OK) {
+ LOG_DEBUG("Error Read failed: read flash mode register");
+ }
+
+ // Clear flash wait state field
+ fmr &= 0xfffff0ff;
+
+ // set FWS (flash wait states) field in the FMR (flash mode register)
+ fmr |= (pPrivate->flash_wait_states << 8);
+
+ LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
+ r = target_write_u32(pPrivate->pBank->target,
pPrivate->controller_address, fmr);
+ if (r != ERROR_OK) {
+ LOG_DEBUG("Error Write failed: set flash mode register");
+ }
LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned
int)(adr));
r = target_write_memory(pPrivate->pChip->target,
--
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