Dear list,
I have already posted the attached script some weeks ago.
It enables the PLL of the STM32F107 and thus configures
the MCU to run at 72 MHz which allows for higher JTAG speeds.
Since this should be useful for everybody, I would like to
contribute it to OpenOCD. However, I am not sure how to integrate
it. One idea is to conditionally call it from scripts/target
/stm32f1x.cfg. Comments and alternative suggestions are highly
appreciated.
Regards,
Simon
# Enable PLL2 and PLL (as in CMSIS system_stm32f10x.c)
# and clock system with 72 Mhz
#
# Set JTAG clock to 6 MHz
$_TARGETNAME configure -event reset-init {
# RCC_CR reset value: 0x??83
# RCC_CR -> RCC_CR_HSEON
mww 0x40021000 0x10083
sleep 10
# FLASH_ACR reset value: 0x30
# FLASH_ACR -> FLASH_ACR_PRFTBE, FLASH_ACR_LATENCY_2
mww 0x40022000 0x32
# RCC_CFGR reset value: 0x0
# RCC_CFGR -> RCC_CFGR_HPRE_DIV1, RCC_CFGR_PPRE2_DIV1,
RCC_CFGR_PPRE1_DIV2
mww 0x40021004 0x400
# RCC_CFGR2 reset value: 0x0
# RCC_CFGR2 -> RCC_CFGR2_PREDIV2_DIV5, RCC_CFGR2_PLL2MUL8,
# RCC_CFGR2_PREDIV1SRC_PLL2, RCC_CFGR2_PREDIV1_DIV5
mww 0x4002102c 0x10644
# RCC_CR -> RCC_CR_PLL2ON
mww 0x40021000 0x4010083
sleep 10
# RCC_CFGR -> PLLCLK = PREDIV1 * 9 = 72 MHz
mww 0x40021004 0x1d0400
# RCC_CR -> RCC_CR_PLLON
mww 0x40021000 0x5010083
sleep 10
# RCC_CR -> RCC_CFGR_SW_PLL
mww 0x40021004 0x1d0402
sleep 10
adapter_khz 6000
}
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