the srst line will be held high or low according to the interface you're using. the ADBUS on the minimodule is like the flyswatter: X X SRST X TMS TDO TDI TCK (AD7 to AD0) the minimodule inits the srst line high. srst line is ADBUS5, so that's nSRST = 0x20 if only srst is used during reset, then the minimodule_reset function is called first with trst==0 and srst==1 to assert a reset, and then with trst==0 and srst==0 to de-assert it. so it goes: normally: 0x20 during reset: 0x00 after reset: 0x20
srst is pulled low and then back up, and it stays there. the other gpio pins are tri-stated unless you do something with them. if you do not want the other gpio pins (ACBUS and ADBUS 7 and 6) to be tristated, then you can use tomek's bitbang stuff. it allows you to handle the other gpio pins and set them hi or low. i've been trying it and it works fine. it's not merged yet, but i hope it will be soon :) On Fri, Jul 8, 2011 at 10:07 AM, Matthew Lai <cyberf...@wecheer.com> wrote: > Ah! I see. > > I guess it's fine as long as OpenOCD either tristates or drive high the > reset lines when it's not doing anything. > > Is that the case? > > Thanks! > Matthew > > On 7/8/2011 9:51 AM, Phil Fong wrote: > > ________________________________ > I'm trying to embed a FT2232D based programmer into my board with a STM32 > (Cortex-M3 MCU). > > I want the programmer to be compatible with jtagkey, so I looked at > schematics of compaible designs. > > I noticed that while the JTAG signals (TCK, TDI, TDO, TMS) are only buffered > when translation is necessary, the SRST and TRST signals are always > tri-state buffered, with OE going into the FTDI chip. > > Is there a reason for that? Can I omit the buffers? > > > Since you are embedding the JTAG interface with the target, you can tell if > buffering is needed. We just went through a similar exercise and you can > pretty much hook everything up directly and use the FTDI MiniModule layout > (see commit from Rodrigo Rosa) if you target circuit is right. > > Also, I heard it's possible to omit the TRST signal and only keep the SRST > signal, because system reset will also reset the TAP controller. Is that > true? Are there problems with that? > > TRST is optional since you can reset the JTAG TAP state machine with > clocking TCK which TMS=1. > SRST might be needed for other reasons. For example some chips need it as > part of some kind of flash / code protection enable/disable. > > Phil > > > > _______________________________________________ > Openocd-development mailing list > Openocd-development@lists.berlios.de > https://lists.berlios.de/mailman/listinfo/openocd-development > > -- Rodrigo. _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
